A High-Performance and Low-Complexity 5G LDPC Decoder: Algorithm and Implementation

5G New Radio (NR) has stringent demands on both performance and complexity for the design of low-density parity-check (LDPC) decoding algorithms and corresponding VLSI implementations. Furthermore, decoders must fully support the wide range of all 5G NR blocklengths and code rates, which is a significant challenge. In this paper, we present a high-performance and low-complexity LDPC decoder, tailor-made to fulfill the 5G requirements. First, to close the gap between belief propagation (BP) decoding and its approximations in hardware, we propose an extension of adjusted min-sum decoding, called generalized adjusted min-sum (GA-MS) decoding. This decoding algorithm flexibly truncates the incoming messages at the check node level and carefully approximates the non-linear functions of BP decoding to balance the error-rate and hardware complexity. Numerical results demonstrate that the proposed fixed-point GAMS has only a minor gap of 0.1 dB compared to floating-point BP under various scenarios of 5G standard specifications. Secondly, we present a fully reconfigurable 5G NR LDPC decoder implementation based on GA-MS decoding. Given that memory occupies a substantial portion of the decoder area, we adopt multiple data compression and approximation techniques to reduce 42.2% of the memory overhead. The corresponding 28nm FD-SOI ASIC decoder has a core area of 1.823 mm2 and operates at 895 MHz. It is compatible with all 5G NR LDPC codes and achieves a peak throughput of 24.42 Gbps and a maximum area efficiency of 13.40 Gbps/mm2 at 4 decoding iterations.Comment: 14 pages, 14 figure

Research on energy-efficient VLSI decoder for LDPC code

制度:新 ; 報告番号:甲3742号 ; 学位の種類:博士(工学) ; 授与年月日:2012/9/15 ; 早大学位記番号:新6113Waseda Universit

Viterbi Accelerator for Embedded Processor Datapaths

We present a novel architecture for a lightweight Viterbi accelerator that can be tightly integrated inside an embedded processor. We investigate the accelerator’s impact on processor performance by using the EEMBC Viterbi benchmark and the in-house Viterbi Branch Metric kernel. Our evaluation based on the EEMBC benchmark shows that an accelerated 65-nm 2.7-ns processor datapath is 20% larger but 90% more cycle efficient than a datapath lacking the Viterbi accelerator, leading to an 87% overall energy reduction and a data throughput of 3.52 Mbit/s

An Architecture for High Data Rate Very Low Frequency Communication

Very low frequency (VLF) communication is used for long range shore-to-ship broadcasting applications. This paper proposes an architecture for high data rate VLF communication using Gaussian minimum shift keying (GMSK) modulation and low delay parity check (LDPC) channel coding. Non-data aided techniques are designed and used for carrier phase synchronization, symbol timing recovery, and LDPC code frame synchronization. These require the estimation of the operative Eb/N0 for which a kurtosis based algorithm is used. Also, a method for modeling the probability density function of the received signal under the bit condition is presented in this regard. The modeling of atmospheric radio noise (ARN) that corrupts VLF signals is described and an algorithm for signal enhancement in the presence of ARN in given. The BER performance of the communication system is evaluated for bit rates of 400 bps, 600 bps, and 800 bps for communication bandwidth of ~200 Hz.Defence Science Journal, 2013, 63(1), pp.25-33, DOI:http://dx.doi.org/10.14429/dsj.63.376