339 research outputs found

    An accurate, trimless, high PSRR, low-voltage, CMOS bandgap reference IC

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    Bandgap reference circuits are used in a host of analog, digital, and mixed-signal systems to establish an accurate voltage standard for the entire IC. The accuracy of the bandgap reference voltage under steady-state (dc) and transient (ac) conditions is critical to obtain high system performance. In this work, the impact of process, power-supply, load, and temperature variations and package stresses on the dc and ac accuracy of bandgap reference circuits has been analyzed. Based on this analysis, the a bandgap reference that 1. has high dc accuracy despite process and temperature variations and package stresses, without resorting to expensive trimming or noisy switching schemes, 2. has high dc and ac accuracy despite power-supply variations, without using large off-chip capacitors that increase bill-of-material costs, 3. has high dc and ac accuracy despite load variations, without resorting to error-inducing buffers, 4. is capable of producing a sub-bandgap reference voltage with a low power-supply, to enable it to operate in modern, battery-operated portable applications, 5. utilizes a standard CMOS process, to lower manufacturing costs, and 6. is integrated, to consume less board space has been proposed. The functionality of critical components of the system has been verified through prototypes after which the performance of the complete system has been evaluated by integrating all the individual components on an IC. The proposed CMOS bandgap reference can withstand 5mA of load variations while generating a reference voltage of 890mV that is accurate with respect to temperature to the first order. It exhibits a trimless, dc 3-sigma accuracy performance of 0.84% over a temperature range of -40°C to 125°C and has a worst case ac power-supply ripple rejection (PSRR) performance of 30dB up to 50MHz using 60pF of on-chip capacitance. All the proposed techniques lead to the development of a CMOS bandgap reference that meets the low-cost, high-accuracy demands of state-of-the-art System-on-Chip environments.Ph.D.Committee Chair: Rincon-Mora, Gabriel; Committee Member: Ayazi, Farrokh; Committee Member: Bhatti, Pamela; Committee Member: Leach, W. Marshall; Committee Member: Morley, Thoma

    A sub 1V bandgap reference circuit

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    This thesis proposes a novel technique for a low supply voltage temperature-independent reference voltage. With the scaling of supply voltages, the threshold voltages don’t scale proportionally and thus low supply reference circuits have replaced the conventional bandgap reference circuit. The first chapter of this work discusses the conventional bandgap references (The Widlar and Brokaw references). The terminology used in the bandgap world is introduced here. The second chapter investigates the existing low supply voltage reference circuits with their advantages and the limitations. A table discussing all the investigated circuits is provided towards the end of the chapter as a summary. Chapter Three proposes a novel technique to generate a temperature-independent voltage which does not use an operational amplifier. This chapter also provides a mathematical understanding for behavior of the circuit. Chapter Four talks about two variations of the proposed architecture. These variations are designed in order to improve the performance of the proposed circuit against power supply variations. Each one of them has its own merits and drawbacks. Finally Chapter Five discusses the effects of process variations and transient response of the proposed circuit. A digital trimming scheme using an EE-PROM is proposed to manage almost all of the process variation effects on the circuit

    128 mA CMOS LDO with 108 db PSRR at 2.4 MHz frequency

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    A low dropout (LDO) voltage regulator with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented in this paper. Large 1”F off-chip load capacitor is used to achieve the high PSRR. However, this decreases the gain and pushes the LDO’s output pole to lower frequency causing the circuit to become unstable. The proposed LDO uses rail-to-rail folded cascode amplifier to compensate the gain and stability problems. 2nd order curvature characteristic is used in bandgap voltage reference circuit that is applied at the input of the amplifier to minimize the TC. The characteristic is achieved by implementing MOSFET transistors operate in weak and strong inversions. The LDO is designed using 0.18”m CMOS technology and achieves a constant 1.8V output voltage for input voltages from 3.2V to 5V and load current up to a 128mA at temperature between -40°C to 125°C. The proposed LDO is targeted for RF application which has stringent requirement on noise rejection over a broad range of frequency

    Current Feedback-Based High Load Current Low Drop-Out Voltage Regulator in 65-nm CMOS Technology

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    The motivation for this paper was to design a current feedback-based high load current, low drop-out (LDO) voltage regulator. A bandgap voltage reference (BGR) was also designed in conjunction with the LDO to simulate realistic environments. The schematic was designed with Cadence Virtuoso Schematic XL, using the Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS library, used for Internet of Things (IoT) System on Chip (SoC) applications. The proposed capacitor-less LDO with BGR provided an average temperature coefficient (TC) of 13.34 ppm/℃ within the range of -40 to 125 ℃. This was in accordance with military standards to gain a higher stability and power supply rejection ratio (PSRR). The proposed capacitor-less LDO also achieved a 200 mA load current with an error percentage of 0.246% and a -21.47 dB PSRR at 100 KHz with a current based structure. This thesis concluded with the application of capacitor-less LDO in medical IoT devices, followed by the future of medical device development

    Design of an output-capacitorless low-dropout regulator for power management applications

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    This article aims to present the design of a 4.5-V, 450-mA low drop-out (LDO) voltage linear regulator based on a twostage cascoded operational transconductance amplifier (OTA) as error amplifier. The aforementioned two-stage OTA is designed with cascoded current mirroring technique to boost up the output impedance. The proposed OTA has a DC gain of 101 dB under no load condition. The designed reference voltage included in the LDO regulator is provided by a band gap reference with the temperature coefficient (TÂż) of 0.025 mV/ÂșC. The proposed LDO regulator has a maximum drop-out voltage of 0.5 V @ 450 mA of load current, and has the worst case power supply rejection ratio (PSRR) of [54.5 dB, 34.3 dB] @ [100 Hz, 10 kHz] in full load condition. All the proposed circuits are designed using a 0.35 ”m CMOS technology. The design is checked in order to corroborate its performance for wide range of input voltage, founding that the circuit design works fine meeting all the initial specification requirements.Postprint (published version

    A fully on-chip LDO voltage regulator with 37 dB PSRR at 1 MHz for remotely powered biomedical implants

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    This article presents a fully on-chip low-power LDO voltage regulator dedicated to remotely powered wireless cortical implants. This regulator is stable over the full range of alternating load current and provides fast load regulation achieved by applying a time-domain design methodology. Moreover, a new compensation technique is proposed and implemented to improve PSRR beyond the performance levels which can be obtained using the standard cascode compensation technique. Measurement results show that the regulator has a load regulation of 0.175 V/A, a line regulation of 0.024%, and a PSRR of 37 dB at 1MHz power carrier frequency. The output of the regulator settles within 10-bit accuracy of the nominal voltage (1.8 V) within 1.6ÎŒs, at full load transition. The total ground current including the bandgap reference circuit is 28ÎŒA and the active chip area measures 290ÎŒm×360ÎŒm in a 0.18ÎŒm CMOS technolog

    Output-capacitorless low-dropout regulator for power management applications

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    This article aims to present the design of a 4.5-V, 450-mA low drop-out (LDO) voltage linear regulator based on a two-stage cascoded operational transconductance amplifier (OTA) as error amplifier. The aforementioned two-stage OTA is designed with cascoded current mirroring technique to boost up the output impedance. The proposed OTA has a DC gain of 101 dB under no load condition. The designed reference voltage included in the LDO regulator is provided by a band gap reference with the temperature coefficient (TÂż) of 0.025 mV/ÂșC. The proposed LDO regulator has a maximum drop-out voltage of 0.5 V @ 450 mA of load current, and has the worst case power supply rejection ratio (PSRR) of [54.5 dB, 34.3 dB] @ [100 Hz, 10 kHz] in full load condition. All the proposed circuits are designed using a 0.35 ”m CMOS technology. The design is checked in order to corroborate its performance for wide range of input voltage, founding that the circuit design works fine meeting all the initial specification requirements.Postprint (published version

    Design consideration in low dropout voltage regulator for batteryless power management unit

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    Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39Âș of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology
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