7 research outputs found
Analysis and Evaluation of PUF-based SoC Designs for Security Applications
This paper presents a critical analysis and statistical evaluation of two categories of Physically Unclonable Functions (PUFs): ring oscillator PUF and a new proposed adapted latch based PUF. The main contribution is that of measuring the properties of PUF which provide the basic information for using them in security applications. The original method involved the conceptual design of adapted latch based PUFs and ring oscillator PUFs in combination with peripheral devices in order to create an environment for experimental analysis of PUF properties. Implementation, testing and analysis of results followed. This approach has applications on high level security
Compact Field Programmable Gate Array Based Physical Unclonable Functions Circuits
The Physical Unclonable Functions (PUFs) is a candidate to provide a secure solid root source for identification and authentication applications. It is precious for FPGA-based systems, as FPGA designs are vulnerable to IP thefts and cloning. Ideally, the PUFs should have strong random variations from one chip to another, and thus each PUF is unique and hard to replicate. Also, the PUFs should be stable over time so that the same challenge bits always yield the same result. Correspondingly, one of the major challenges for FPGA-based PUFs is the difficulty of avoiding systematic bias in the integrated circuits but also pulling out consistent characteristics as the PUF at the same time. This thesis discusses several compact PUF structures relying on programmable delay lines (PDLs) and our novel intertwined programmable delays (IPD). We explore the strategy to extract the genuinely random PUF from these structures by minimizing the systematic biases. Yet, our methods still maintain very high reliability. Furthermore, our proposed designs, especially the TERO-based PUFs, show promising resilience to machine learning (ML) attacks. We also suggest the bit-bias metric to estimate PUF’s complexity quickly
Lightweight Silicon-based Security: Concept, Implementations, and Protocols
Advancement in cryptography over the past few decades has enabled a spectrum of security mechanisms and protocols for many applications. Despite the algorithmic security of classic cryptography, there are limitations in application and implementation of standard security methods in ultra-low energy and resource constrained
systems. In addition, implementations of standard cryptographic methods can be
prone to physical attacks that involve hardware level invasive or non-invasive attacks.
Physical unclonable functions (PUFs) provide a complimentary security paradigm for a number of application spaces where classic cryptography has shown to be inefficient or inadequate for the above reasons. PUFs rely on intrinsic device-dependent
physical variation at the microscopic scale. Physical variation results from imperfection
and random fluctuations during the manufacturing process which impact each device’s characteristics in a unique way. PUFs at the circuit level amplify and capture
variation in electrical characteristics to derive and establish a unique device-dependent
challenge-response mapping.
Prior to this work, PUF implementations were unsuitable for low power applications
and vulnerable to wide range of security attacks. This doctoral thesis presents a coherent framework to derive formal requirements to design architectures and protocols
for PUFs. To the best of our knowledge, this is the first comprehensive work that
introduces and integrates these pieces together. The contributions include an introduction
of structural requirements and metrics to classify and evaluate PUFs, design
of novel architectures to fulfill these requirements, implementation and evaluation of
the proposed architectures, and integration into real-world security protocols.
First, I formally define and derive a new set of fundamental requirements and
properties for PUFs. This work is the first attempt to provide structural requirements
and guideline for design of PUF architectures. Moreover, a suite of statistical properties of PUF responses and metrics are introduced to evaluate PUFs.
Second, using the proposed requirements, new and efficient PUF architectures are
designed and implemented on both analog and digital platforms. In this work, the
most power efficient and smallest PUF known to date is designed and implemented on ASICs that exploits analog variation in sub-threshold leakage currents of MOS
devices. On the digital platform, the first successful implementation of Arbiter-PUF on FPGA was accomplished in this work after years of unsuccessful attempts by the research community. I introduced a programmable delay tuning mechanism with pico-second resolution which serves as a key component in implementation of the
Arbiter-PUF on FPGA. Full performance analysis and comparison is carried out through comprehensive device simulations as well as measurements performed on a
population of FPGA devices.
Finally, I present the design of low-overhead and secure protocols using PUFs for integration in lightweight identification and authentication applications. The new protocols are designed with elegant simplicity to avoid the use of heavy hash operations
or any error correction. The first protocol uses a time bound on the authentication process while second uses a pattern-matching index-based method to thwart reverseengineering
and machine learning attacks. Using machine learning methods during
the commissioning phase, a compact representation of PUF is derived and stored in a database for authentication
Development of a new trigger system for spin-filtering studies
Polarized antiprotons allow unique access to a number of fundamental physics observables. One
example is the transversity distribution which is the last missing piece to complete the knowledge
of the nucleon partonic structure at leading twist in the QCD-based parton model. The transversity
is directly measurable via Drell-Yan production in double polarized antiproton-proton collisions.
This and a multitude of other findings, which are accessible via ~p ~p scattering experiments, led the
Polarized Antiproton eXperiments (PAX) Collaboration to propose such investigations at the High
Energy Storage Ring (HESR) of the Facility for Antiproton and Ion Research (FAIR). Futhermore
the production of intense polarized antiproton beams is still an unsolved problem, which is the
core of the PAX proposal.
In this frame, an intense work on the feasibility of this ambitious project is going on at COSY
(COoler SYnchrotron of the Institut für KernPhysik –IKP– of the Forschungs Zentrum Jülich) (FZJ)
where the work of this thesis has been performed.
Presently, the only available method to polarize an antiproton beam is by means of the mechanism
of spin-filtering exploiting the spin dependence of the (p p) interaction via the repeated
interaction with a polarized hydrogen target. Since the total cross section is different for parallel
and antiparallel orientation of the beam particle spins relative to the direction of the target polarization,
one spin direction is depleted faster than the other, so that the circulating beam becomes
increasingly polarized, while the intensity decreases with time.
A spin-filtering experiment with protons has been prepared and finally realized in 2011 at
the COSY ring in Jülich. Aims of the spin-filtering experiments at COSY performed by the PAX
Collaboration were two. The first was to confirm the present understanding of the spin filtering
processes in storage rings, and the second was the commissioning of the experimental setup, which
will be used for the experiments with the antiprotons.
The major part of my PhD work consisted in the development and commissioning of a new
trigger board to be implemented in the Data Acquisition System (DAQ) of the experiment. The
motivation for the project was the replacement of the existing old-fashioned trigger system based
on NIM logic modules, with a modern system based on FPGA programmable chips. This, also in
perspective of the more complex detection system that the Collaboration is planning to realize for
the future experimental activity.
The trigger board was designed and realized by the electronic workshop of the University of
Ferrara and INFN of Ferrara. My first task was to write the control-software of the board. After that
I performed a series of development and commissioning tests which successfully demonstrated
the full efficiency of the board and gave green light for the implementation of the board in the
experimental setup
PUF Modeling Attacks on Simulated and Silicon Data
We discuss numerical modeling attacks on several proposed strong physical unclonable functions (PUFs). Given a set of challenge-response pairs (CRPs) of a Strong PUF, the goal of our attacks is to construct a computer algorithm which behaves indistinguishably from the original PUF on almost all CRPs. If successful, this algorithm can subsequently impersonate the Strong PUF, and can be cloned and distributed arbitrarily. It breaks the security of any applications that rest on the Strong PUF's unpredictability and physical unclonability. Our method is less relevant for other PUF types such as Weak PUFs. The Strong PUFs that we could attack successfully include standard Arbiter PUFs of essentially arbitrary sizes, and XOR Arbiter PUFs, Lightweight Secure PUFs, and Feed-Forward Arbiter PUFs up to certain sizes and complexities. We also investigate the hardness of certain Ring Oscillator PUF architectures in typical Strong PUF applications. Our attacks are based upon various machine learning techniques, including a specially tailored variant of logistic regression and evolution strategies. Our results are mostly obtained on CRPs from numerical simulations that use established digital models of the respective PUFs. For a subset of the considered PUFs-namely standard Arbiter PUFs and XOR Arbiter PUFs-we also lead proofs of concept on silicon data from both FPGAs and ASICs. Over four million silicon CRPs are used in this process. The performance on silicon CRPs is very close to simulated CRPs, confirming a conjecture from earlier versions of this work. Our findings lead to new design requirements for secure electrical Strong PUFs, and will be useful to PUF designers and attackers alike.National Science Foundation (U.S.) (Grant CNS 0923313)National Science Foundation (U.S.) (Grant CNS 0964641
Comprehensive study of physical unclonable functions on FPGAs: correlation driven Implementation, deep learning modeling attacks, and countermeasures
For more than a decade and a half, Physical Unclonable Functions (PUFs) have been
presented as a promising hardware security primitive. The idea of exploiting variabilities
in hardware fabrication to generate a unique fingerprint for every silicon chip introduced a
more secure and cheaper alternative. Other solutions using non-volatile memory to store
cryptographic keys, require additional processing steps to generate keys externally, and
secure environments to exchange generated keys, which introduce many points of attack
that can be used to extract the secret keys.
PUFs were addressed in the literature from different perspectives. Many publications
focused on proposing new PUF architectures and evaluation metrics to improve security
properties like response uniqueness per chip, response reproducibility of the same PUF
input, and response unpredictability using previous input/response pairs. Other research
proposed attack schemes to clone the response of PUFs, using conventional machine learning
(ML) algorithms, side-channel attacks using power and electromagnetic traces, and fault
injection using laser beams and electromagnetic pulses. However, most attack schemes to
be successful, imposed some restrictions on the targeted PUF architectures, which make
it simpler and easier to attack. Furthermore, they did not propose solid and provable
enhancements on these architectures to countermeasure the attacks. This leaves many
open questions concerning how to implement perfect secure PUFs especially on FPGAs,
how to extend previous modeling attack schemes to be successful against more complex
PUF architectures (and understand why modeling attacks work) and how to detect and
countermeasure these attacks to guarantee that secret data are safe from the attackers.
This Ph.D. dissertation contributes to the state of the art research on physical unclonable
functions in several ways. First, the thesis provides a comprehensive analysis of the implementation of secure PUFs on FPGAs using manual placement and manual routing
techniques guided by new performance metrics to overcome FPGAs restrictions with minimum
hardware and area overhead. Then the impact of deep learning (DL) algorithms is
studied as a promising modeling attack scheme against complex PUF architectures, which
were reported immune to conventional (ML) techniques. Furthermore, it is shown that
DL modeling attacks successfully overcome the restrictions imposed by previous research
even with the lack of accurate mathematical models of these PUF architectures. Finally,
this comprehensive analysis is completed by understanding why deep learning attacks are
successful and how to build new PUF architectures and extra circuitry to thwart these types
of attacks. This research is important for deploying cheap and efficient hardware security
primitives in different fields, including IoT applications, embedded systems, automotive
and military equipment. Additionally, it puts more focus on the development of strong intrinsic PUFs which are widely proposed and deployed in many security protocols used
for authentication, key establishment, and Oblivious transfer protocols
Radio Communications
In the last decades the restless evolution of information and communication technologies (ICT) brought to a deep transformation of our habits. The growth of the Internet and the advances in hardware and software implementations modified our way to communicate and to share information. In this book, an overview of the major issues faced today by researchers in the field of radio communications is given through 35 high quality chapters written by specialists working in universities and research centers all over the world. Various aspects will be deeply discussed: channel modeling, beamforming, multiple antennas, cooperative networks, opportunistic scheduling, advanced admission control, handover management, systems performance assessment, routing issues in mobility conditions, localization, web security. Advanced techniques for the radio resource management will be discussed both in single and multiple radio technologies; either in infrastructure, mesh or ad hoc networks