1,339 research outputs found

    An accurate, trimless, high PSRR, low-voltage, CMOS bandgap reference IC

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    Bandgap reference circuits are used in a host of analog, digital, and mixed-signal systems to establish an accurate voltage standard for the entire IC. The accuracy of the bandgap reference voltage under steady-state (dc) and transient (ac) conditions is critical to obtain high system performance. In this work, the impact of process, power-supply, load, and temperature variations and package stresses on the dc and ac accuracy of bandgap reference circuits has been analyzed. Based on this analysis, the a bandgap reference that 1. has high dc accuracy despite process and temperature variations and package stresses, without resorting to expensive trimming or noisy switching schemes, 2. has high dc and ac accuracy despite power-supply variations, without using large off-chip capacitors that increase bill-of-material costs, 3. has high dc and ac accuracy despite load variations, without resorting to error-inducing buffers, 4. is capable of producing a sub-bandgap reference voltage with a low power-supply, to enable it to operate in modern, battery-operated portable applications, 5. utilizes a standard CMOS process, to lower manufacturing costs, and 6. is integrated, to consume less board space has been proposed. The functionality of critical components of the system has been verified through prototypes after which the performance of the complete system has been evaluated by integrating all the individual components on an IC. The proposed CMOS bandgap reference can withstand 5mA of load variations while generating a reference voltage of 890mV that is accurate with respect to temperature to the first order. It exhibits a trimless, dc 3-sigma accuracy performance of 0.84% over a temperature range of -40°C to 125°C and has a worst case ac power-supply ripple rejection (PSRR) performance of 30dB up to 50MHz using 60pF of on-chip capacitance. All the proposed techniques lead to the development of a CMOS bandgap reference that meets the low-cost, high-accuracy demands of state-of-the-art System-on-Chip environments.Ph.D.Committee Chair: Rincon-Mora, Gabriel; Committee Member: Ayazi, Farrokh; Committee Member: Bhatti, Pamela; Committee Member: Leach, W. Marshall; Committee Member: Morley, Thoma

    An Ultra-Low-Power RFID/NFC Frontend IC Using 0.18 μm CMOS Technology for Passive Tag Applications

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    Battery-less passive sensor tags based on RFID or NFC technology have achieved much popularity in recent times. Passive tags are widely used for various applications like inventory control or in biotelemetry. In this paper, we present a new RFID/NFC frontend IC (integrated circuit) for 13.56 MHz passive tag applications. The design of the frontend IC is compatible with the standard ISO 15693/NFC 5. The paper discusses the analog design part in details with a brief overview of the digital interface and some of the critical measured parameters. A novel approach is adopted for the demodulator design, to demodulate the 10% ASK (amplitude shift keying) signal. The demodulator circuit consists of a comparator designed with a preset offset voltage. The comparator circuit design is discussed in detail. The power consumption of the bandgap reference circuit is used as the load for the envelope detection of the ASK modulated signal. The sub-threshold operation and low-supply-voltage are used extensively in the analog design—to keep the power consumption low. The IC was fabricated using 0.18 μ m CMOS technology in a die area of 1.5 mm × 1.5 mm and an effective area of 0.7 m m 2 . The minimum supply voltage desired is 1.2 V, for which the total power consumption is 107 μ W. The analog part of the design consumes only 36 μ W, which is low in comparison to other contemporary passive tags ICs. Eventually, a passive tag is developed using the frontend IC, a microcontroller, a temperature and a pressure sensor. A smart NFC device is used to readout the sensor data from the tag employing an Android-based application software. The measurement results demonstrate the full passive operational capability. The IC is suitable for low-power and low-cost industrial or biomedical battery-less sensor applications. A figure-of-merit (FOM) is proposed in this paper which is taken as a reference for comparison with other related state-of-the-art researches

    Low-power switched capacitor voltage reference

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    Low-power analog design represents a developing technological trend as it emerges from a rather limited range of applications to a much wider arena affecting mainstream market segments. It especially affects portable electronics with respect to battery life, performance, and physical size. Meanwhile, low-power analog design enables technologies such as sensor networks and RFID. Research opportunities abound to exploit the potential of low power analog design, apply low-power to established fields, and explore new applications. The goal of this effort is to design a low-power reference circuit that delivers an accurate reference with very minimal power consumption. The circuit and device level low-power design techniques are suitable for a wide range of applications. To meet this goal, switched capacitor bandgap architecture was chosen. It is the most suitable for developing a systematic, and groundup, low-power design approach. In addition, the low-power analog cell library developed would facilitate building a more complex low-power system. A low-power switched capacitor bandgap was designed, fabricated, and fully tested. The bandgap generates a stable 0.6-V reference voltage, in both the discrete-time and continuous-time domain. The system was thoroughly tested and individual building blocks were characterized. The reference voltage is temperature stable, with less than a 100 ppm/°C drift, over a --60 dB power supply rejection, and below a 1 [Mu]A total supply current (excluding optional track-and-hold). Besides using it as a voltage reference, potential applications are also described using derivatives of this switched capacitor bandgap, specifically supply supervisory and on-chip thermal regulation

    Model of Switched-Capacitor Programmable Voltage Reference: Optimization for Ultra Low-Power Applications

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    This paper proposes an analytical model for the optimized design of a switched-capacitor programmable voltage reference (SC-PVREF). This PVREF topology guarantees a straightforward design, easy portability across different technology nodes, and does not require any special technology option. The developed model allows the study of the trade-offs and the a priori evaluation of the system performance. Circuit optimization is carried out with MATLAB and permits SC-PVREF to achieve current consumptions of tens of nanoampere, suitable for ultra low-power applications

    Chip Implementation with a Combined Wireless Temperature Sensor and Reference Devices Based on the DZTC Principle

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    This paper presents a novel CMOS wireless temperature sensor design in order to improve the sensitivity and linearity of our previous work on such devices. Based on the principle of CMOS double zero temperature coefficient (DZTC) points, a combined device is first created at the chip level with two voltage references, one current reference, and one temperature sensor. It was successfully fabricated using the 0.35 μm CMOS process. According to the chip results in a wide temperature range from −20 °C to 120 °C, two voltage references can provide temperature-stable outputs of 823 mV and 1,265 mV with maximum deviations of 0.2 mV and 8.9 mV, respectively. The result for the current reference gives a measurement of 23.5 μA, with a maximum deviation of 1.2 μA. The measurements also show that the wireless temperature sensor has good sensitivity of 9.55 mV/°C and high linearity of 97%. The proposed temperature sensor has 4.15-times better sensitivity than the previous design. Moreover, to facilitate temperature data collection, standard wireless data transmission is chosen; therefore, an 8-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) and a 433 MHz wireless transmitter are also integrated in this chip. Sensing data from different places can be collected remotely avoiding the need for complex wire lines

    CMOS analog-digital circuit components for low power applications

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    Dissertação de mestrado em Micro and NanoelectronicsThis dissertation presents a study in the area of mixed analog/digital CMOS power extraction circuits for energy harvester. The main contribution of this work is the realization of low power consumption and high efficient circuit components employable in a management circuit for piezoelectricbased energy harvester. This thesis focuses on the development of current references and operational amplifiers addressing low power demands. A brief literature review is conducted on the components necessary for the power extraction circuit, including introduction to CMOS technology design and research of known low power circuits. It is presented with multiple implementations for voltage and current references, as well for operational amplifier designs. A self-biased current reference, capable of driving the remaining harvesting circuit, is designed and verified. A novel operational amplifier is proposed by the use of a minimum current selector circuit topology. It is a three-stage amplifier with an AB class output stage, comprised by a translinear circuit. The circuit is designed, taking into consideration noise reduction. The circuit components are designed based on the 0.35mm CMOS technology. A physical layout is developed for fabrication purposes. This technology was chosen with consideration of robustness, costliness and performance. The current reference is capable of outputting a stable 12nA current, which may remain stable in a broad range of power supply voltages with a minimum voltage of 1.6V. The operational amplifier operates correctly at voltages as low as 1.5V. The amplifier power consumption is extremely low, around 8mW, with an optimal quiescent current and minimum current preservation in the output stage.A principal contribuição desta dissertação é a implementação de circuitos integrados de muito baixo consumo e alta eficiência, prontos a ser implementados num circuito de extração de energia com base num elemento piezoelétrico. Esta tese foca-se no desenvolvimento de um circuito de referência de corrente e um amplificador operacional com baixa exigência de consumo. Uma revisão da literatura é realizada, incluindo introdução à tecnologia Complementary Metal-Oxide-Semiconductor (CMOS), e implementação de conhecidos circuitos de baixo consumo. Várias implementações de referência de tensão e corrente são consideradas, e amplificadores operacionais também. Uma referência de corrente auto polarizada com extremo baixo consumo é desenvolvida e verificada. Um amplificador operacional original é proposto com uma topologia de seleção de corrente mínima. Este circuito é constituído por três estágios, com um estágio de saída de classe AB, e um circuito translinear. O circuito tem em consideração redução de ruído na sua implementação. Os circuitos são desenvolvidos com base na tecnologia 0.35mm CMOS. Uma layout foi também desenhada com o propósito de fabricação. A tecnologia foi escolhida tendo em conta o seu custo versus desempenho. A referência de corrente produz uma corrente de 12nA, permanecendo estável para tensões de alimentação de variáveis, com uma tensão mínima de 1.6V. O circuito mostra um coeficiente de temperatura satisfatório. O amplificador operacional funciona com tensão de alimentação mínima de 1.5V, com um consumo baixo de 8mW, com uma corrente mínima mantida no estágio de saída

    Limits on Fundamental Limits to Computation

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    An indispensable part of our lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the last fifty years. Such Moore scaling now requires increasingly heroic efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and enrich our understanding of integrated-circuit scaling, we review fundamental limits to computation: in manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, we recall how some limits were circumvented, compare loose and tight limits. We also point out that engineering difficulties encountered by emerging technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl

    Next Generation of Ultra-High Precision Amplifiers

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