A High Step Up Converter With A Voltage Multiplier Module For A Pv System

A novel high step-up high-efficiency interleaved converter with voltage multiplier module for renewable energy system, is proposed in this paper. A new voltage multiplier module composed which is having switched capacitors and coupled inductors, with its combination a conventional interleaved boost converter obtains high step-up gain without operating at extreme duty ratio is designed. This proposed converter reduces the current stress and also reduces constrains the input current ripple, which decreases the conduction losses and lengthens the lifetime of the input source. Hence, large voltage spikes across the main switches are reduced, and hence the efficiency will be improved. Even the low voltage stress makes the low-voltage-rated MOSFETs be adopted for reductions of conduction losses and cost. The proposed circuit designed with 40-V input voltage, 380-V output, and 1000-W output power in the MATLAB/SIMULINK software, and is operated to verify its performance. The highest efficiency is 97.1%

Boost Interleaved Converter Integrated Voltage Multiplier Module for Renewable Energy System

This document presents a high step-up converter, which is apt for renewable energy system. Through a voltage multiplier unit composed of switched capacitors and coupled inductors, a conventional interleaved boost converter obtains high step-up gain without operating at extreme duty ratio. The design of the proposed converter not only reduces the current stress but also constrains the input current ripple, which decreases the conduction losses and lengthens the lifetime of the input source. In addition, due to the lossless passive clamp performance, leakage energy is recycled to the output terminal. Hence, large voltage spikes across the main switches are alleviated, and the efficiency is improved. Even the low voltage stress makes the low-voltage-rated MOSFETs be adopted for reductions of conduction losses and cost. Finally, the prototype circuit with 40-V input voltage, 380-V output, and 1000-W output power is operated to verify its performance. The highest efficiency is 97.1%. Index Terms - Voltage multiplier module. Boost–flyback converter, high step-up, photovoltaic (PV) system

Advanced topologies of high step-up DC-DC converters for renewable energy applications

This research is focused on developing several advanced topologies of high step-up DC-DC converters to connect low-voltage renewable energy (RE) sources, such as photovoltaic (PV) panels and fuel cells (FCs), into a high-voltage DC bus in renewable energy applications. The proposed converters are based on the combinations of various voltage-boosting (VB) techniques, including interleaved and quadratic structures, switched-capacitor (SC)-based voltage multiplier (VM) cells, and magnetically coupled inductor (CI) and built-in-transformer (BIT). The proposed converters offer outstanding features, including high voltage gain with low or medium duty cycle, a small number of components, low current and voltage stresses on the components, continuous input current with low ripple, and high efficiency. This research includes five new advanced high step-up DC-DC converters with detailed analyses. First, an interleaved converter is presented, which is based on the integration of two three-winding CIs with SC-based VM cells. Second, a dual-switch converter is proposed, which is based on the integration of a single three-winding CI with SC-based VM cells. Third, the SC-based VM cells are utilized to present three new Z-source (ZS)-based converters. Fourth, two double-winding CIs and a three-winding BIT are combined with SC-based VM cells to develop another interleaved high step-up converter. Finally, two double-winding CIs and SC-based VM cells are adopted to devise an interleaved quadratic converter with high voltage gain. The operating and steady-state analyses, design considerations, and a comparison with similar converters in the literature are provided for each converter. In addition, hardware prototypes were fabricated to verify the performance of the proposed converters --Abstract, page iv

Low Voltage Floating Gate MOS Transistor Based Four-Quadrant Multiplier

This paper presents a four-quadrant multiplier based on square-law characteristic of floating gate MOSFET (FGMOS) in saturation region. The proposed circuit uses square-difference identity and the differential voltage squarer proposed by Gupta et al. to implement the multiplication function. The proposed multiplier employs eight FGMOS transistors and two resistors only. The FGMOS implementation of the multiplier allows low voltage operation, reduced power consumption and minimum transistor count. The second order effects caused due to mobility degradation, component mismatch and temperature variations are discussed. Performance of the proposed circuit is verified at ±0.75 V in TSMC 0.18 µm CMOS, BSIM3 and Level 49 technology by using Cadence Spectre simulator

The road to fully integrated DC-DC conversion via the switched-capacitor approach

This paper provides a perspective on progress toward realization of efficient, fully integrated dc-dc conversion and regulation functionality in CMOS platforms. In providing a comparative assessment between the inductor-based and switched-capacitor approaches, the presentation reviews the salient features in effectiveness in utilization of switch technology and in use and implementation of passives. The analytical conclusions point toward the strong advantages of the switched-capacitor (SC) approach with respect to both switch utilization and much higher energy densities of capacitors versus inductors. The analysis is substantiated with a review of recently developed and published integrated dc-dc converters of both the inductor-based and SC types. © 2012 IEEE

Development of high-gain gaseous photomultipliers for the visible spectral range

We summarize the development of visible-sensitive gaseous photomultipliers, combining a semitransparent bi-alkali photocathode with a state-of-the-art cascaded electron multiplier. The latter has high photoelectron collection efficiency and a record ion blocking capability. We describe in details the system and methods of photocathode production and characterization, their coupling with the electron multiplier and the gaseous-photomultiplier operation and characterization in a continuous mode. We present results on the properties of laboratory-produced K$_2$CsSb, Cs$_3$Sb and Na$_2$KSb photocathodes and report on their stability and QE in gas; K$_2$CsSb photocathodes yielded QE values in Ar/CH$_4$(95/5) above 30% at wavelengths of 360-400 nm. The novel gaseous photomultiplier yielded stable operation at gains of 10$^5$, in continuous operation mode, in 700 Torr of this gas; its sensitivity to single photons was demonstrated. Other properties are described. The successful detection of visible light with this gas-photomultiplier pave ways towards further development of large-area sealed imaging detectors, of flat geometry, insensitive to magnetic fields, which might have significant impact on light detection in numerous fields.Comment: 22 pages, 12 figures, for submission to JINS

Novel Ternary Logic Gates Design in Nanoelectronics

In this paper, standard ternary logic gates are initially designed to considerably reduce static power consumption. This study proposes novel ternary gates based on two supply voltages in which the direct current is eliminated and the leakage current is reduced considerably. In addition, ST-OR and ST-AND are generated directly instead of ST-NAND and ST-NOR. The proposed gates have a high noise margin near V_(DD)/4. The simulation results indicated that the power consumption and PDP underwent a~sharp decrease and noise margin showed a considerable increase in comparison to both one supply and two supply based designs in previous works. PDP is improved in the proposed OR, as compared to one supply and two supply based previous works about 83% and 63%, respectively. Also, a memory cell is designed using the proposed STI logic gate, which has a considerably lower static power to store logic ‘1’ and the static noise margin, as compared to other designs

Asynchronous Circuit Stacking for Simplified Power Management

As digital integrated circuits (ICs) continue to increase in complexity, new challenges arise for designers. Complex ICs are often designed by incorporating multiple power domains therefore requiring multiple voltage converters to produce the corresponding supply voltages. These converters not only take substantial on-chip layout area and/or off-chip space, but also aggregate the power loss during the voltage conversions that must occur fast enough to maintain the necessary power supplies. This dissertation work presents an asynchronous Multi-Threshold NULL Convention Logic (MTNCL) “stacked” circuit architecture that alleviates this problem by reducing the number of voltage converters needed to supply the voltage the ICs operate at. By stacking multiple MTNCL circuits between power and ground, supplying a multiple of VDD to the entire stack and incorporating simple control mechanisms, the dynamic range fluctuation problem can be mitigated. A 130nm Bulk CMOS process and a 32nm Silicon-on-Insulator (SOI) CMOS process are used to evaluate the theoretical effect of stacking different circuitry while running different workloads. Post parasitic physical implementations are then carried out in the 32nm SOI process for demonstrating the feasibility and analyzing the advantages of the proposed MTNCL stacking architecture

A CMOS analog continuous-time delay line with adaptive delay-time control

A CMOS analog continuous-time delay line composed of cascaded first-order current-domain all-pass sections is discussed. Each all-pass section consists of CMOS transistors and a single capacitor. The operation is based on the square-law characteristic of an MOS transistor in saturation. The delay time per section can either be controlled by an external voltage or locked to an external reference frequency by means of a control system which features a large capture range. Experimental verification has been performed on two setups: an integrated cascade of 26 identical all-pass sections and a frequency-locking system breadboard built around two identical on-chip all-pass section

A wideband linear tunable CDTA and its application in field programmable analogue array

This document is the Accepted Manuscript version of the following article: Hu, Z., Wang, C., Sun, J. et al. ‘A wideband linear tunable CDTA and its application in field programmable analogue array’, Analog Integrated Circuits and Signal Processing, Vol. 88 (3): 465-483, September 2016. Under embargo. Embargo end date: 6 June 2017. The final publication is available at Springer via https://link.springer.com/article/10.1007%2Fs10470-016-0772-7 © Springer Science+Business Media New York 2016In this paper, a NMOS-based wideband low power and linear tunable transconductance current differencing transconductance amplifier (CDTA) is presented. Based on the NMOS CDTA, a novel simple and easily reconfigurable configurable analogue block (CAB) is designed. Moreover, using the novel CAB, a simple and versatile butterfly-shaped FPAA structure is introduced. The FPAA consists of six identical CABs, and it could realize six order current-mode low pass filter, second order current-mode universal filter, current-mode quadrature oscillator, current-mode multi-phase oscillator and current-mode multiplier for analog signal processing. The Cadence IC Design Tools 5.1.41 post-layout simulation and measurement results are included to confirm the theory.Peer reviewedFinal Accepted Versio