Performance study of voice over frame relay : a thesis presented in partial fulfilment of the requirements for the degree of Master of Engineering in Information Engineering, Massey University, Albany, New Zealand

Frame Relay (FR) represents an important paradigm shift in modern telecommunication. This technology is beginning to evolve from data only application to broad spectrum of multimedia users and potential to provide end users with cost effective transport of voice traffic for intra office communication. In this project the recent development in voice communication over Frame relay is investigated. Simulations were carried out using OPNET, a powerful simulation software. Following the simulation model, a practical design of the LAN-to-LAN connectivity experiment was also done in the Net Lab. From the results of the simulation, Performance measures such as delay, jitter, and throughput are reported. It is evident from the results that real-time voice or video across a frame relay network can provide acceptable performance

A three-stage ATM switch with cell-level path allocation

A method is described for performing routing in three-stage asynchronous transfer mode (ATM) switches which feature multiple channels between the switch modules in adjacent stages. The method is suited to hardware implementation using parallelism to achieve a very short execution time. This allows cell-level routing to be performed, whereby routes are updated in each time slot. The algorithm allows a contention-free routing to be performed, so that buffering is not required in the intermediate stage. An algorithm with this property, which preserves the cell sequence, is referred to as a path allocation algorithm. A detailed description of the necessary hardware is presented. This hardware uses a novel circuit to count the number of cells requesting each output module, it allocates a path through the intermediate stage of the switch to each cell, and it generates a routing tag for each cell, indicating the path assigned to it. The method of routing tag assignment described employs a nonblocking copy network. The use of highly parallel hardware reduces the clock rate required of the circuitry, for a given-switch size. The performance of ATM switches using this path allocation algorithm has been evaluated by simulation, and is described

Optimal Content Placement for En-Route Web Caching

This paper studies the optimal placement of web files for en-route web caching. It is shown that existing placement policies are all solving restricted partial problems of the file placement problem, and therefore give only sub-optimal solutions. A dynamic programming algorithm of low complexity which computes the optimal solution is presented. It is shown both analytically and experimentally that the file-placement solution output by our algorithm outperforms existing en-route caching policies. The optimal placement of web files can be implemented with a reasonable level of cache coordination and management overhead for en-route caching; and importantly, it can be achieved with or without using data prefetching