Analog integrated circuit design in ultra-thin oxide CMOS technologies with significant direct tunneling-induced gate current

The ability to do mixed-signal IC design in a CMOS technology has been a driving force for manufacturing personal mobile electronic products such as cellular phones, digital audio players, and personal digital assistants. As CMOS has moved to ultra-thin oxide technologies, where oxide thicknesses are less than 3 nm, this type of design has been threatened by the direct tunneling of carriers though the gate oxide. This type of tunneling, which increases exponentially with decreasing oxide thickness, is a source of MOSFET gate current. Its existence invalidates the simplifying design assumption of infinite gate resistance. Its problems are typically avoided by switching to a high-&kappa/metal gate technology or by including a second thick(er) oxide transistor. Both of these solutions come with undesirable increases in cost due to extra mask and processing steps. Furthermore, digital circuit solutions to the problems created by direct tunneling are available, while analog circuit solutions are not. Therefore, it is desirable that analog circuit solutions exist that allow the design of mixed-signal circuits with ultra-thin oxide MOSFETs. This work presents a methodology that develops these solutions as a less costly alternative to high-&kappa/metal gate technologies or thick(er) oxide transistors. The solutions focus on transistor sizing, DC biasing, and the design of current mirrors and differential amplifiers. They attempt to minimize, balance, and cancel the negative effects of direct tunneling on analog design in traditional (non-high-&kappa/metal gate) ultra-thin oxide CMOS technologies. They require only ultra-thin oxide devices and are investigated in a 65 nm CMOS technology with a nominal VDD of 1 V and a physical oxide thickness of 1.25 nm. A sub-1 V bandgap voltage reference that requires only ultra-thin oxide MOSFETs is presented (TC = 251.0 ppm/°C). It utilizes the developed methodology and illustrates that it is capable of suppressing the negative effects of direct tunneling. Its performance is compared to a thick-oxide voltage reference as a means of demonstrating that ultra-thin oxide MOSFETs can be used to build the analog component of a mixed-signal system

Scaling the bulk-driven MOSFET into deca-nanometer bulk CMOS technologies

The International Technology Roadmap for Semiconductors predicts that the nominal power supply voltage, VDD, will fall to 0.7 V by the end of the bulk CMOS era. At that time, it is expected that the long-channel threshold voltage of a MOSFET, VT0, will rise to 35.5% of VDD in order to maintain acceptable off-state leakage characteristics in digital systems. Given the recent push for system-on-a-chip integration, this increasing trend in VT0/VDD poses a serious threat to the future of analog design because it causes traditional analog circuit topologies to experience progressively problematic signal swing limitations in each new process generation. To combat the process-scaling-induced signal swing limitations of analog circuitry, researchers have proposed the use of bulk-driven MOSFETs. By using the bulk terminal as an input rather than the gate, the bulk-driven MOSFET makes it possible to extend the applicability of any analog cell to extremely low power supply voltages because VT0 does not appear in the device\u27s input signal path. Since the viability of the bulk-driven technique was first investigated in a 2 um p-well process, there have been numerous reports of low-voltage analog designs incorporating bulk-driven MOSFETs in the literature - most of which appear in technologies with feature sizes larger than 0.18 um. However, as of yet, no effort has been undertaken to understand how sub-micron process scaling trends have influenced the performance of a bulk-driven MOSFET, let alone make the device more adaptable to the deca-nanometer technologies widely used in the analog realm today. Thus, to further the field\u27s understanding of the bulk-driven MOSFET, this dissertation aims to examine the implications of scaling the device into a standard 90 nm bulk CMOS process. This dissertation also describes how the major disadvantages of a bulk-driven MOSFET - i.e., its reduced intrinsic gain, its limited frequency response and its large layout area requirement - can be mitigated through modifications to the device\u27s vertical doping profile and well structure. To gauge the potency of the proposed process changes, an optimized n-type bulk-driven MOSFET has been designed in a standard 90 nm bulk CMOS process via the 2-D device simulator, ATLAS

[Delta] IDDQ testing of a CMOS 12-bit charge scaling digital-to-analog converter

This work presents design, implementation and test of a built-in current sensor (BICS) for ∆IDDQ testing of a CMOS 12-bit charge scaling digital-to-analog converter (DAC). The sensor uses power discharge method for the fault detection. The sensor operates in two modes, the test mode and the normal mode. In the test mode, the BICS is connected to the circuit under test (CUT) which is DAC and detects abnormal currents caused by manufacturing defects. In the normal mode, BICS is isolated from the CUT. The BICS is integrated with the DAC and is implemented in a 0.5 μm n-well CMOS technology. The DAC uses charge scaling method for the design and a low voltage (0 to 2.5 V) folded cascode op-amp. The built-in current sensor (BICS) has a resolution of 0.5 μA. Faults have been introduced into DAC using fault injection transistors (FITs). The method of ∆IDDQ testing has been verified both from simulation and experimental measurements

Techniques for low power analog, digital and mixed signal CMOS integrated circuit design

With the continuously expanding of market for portable devices such as wireless communication devices, portable computers, consumer electronics and implantable medical devices, low power is becoming increasingly important in integrated circuits. The low power design can increase operation time and/or utilize a smaller size and lighter-weight battery. In this dissertation, several low power complementary metal-oxide-semiconductor (CMOS) integrated circuit design techniques are investigated. A metal-oxide-semiconductor field effect transistor (MOSFET) can be operated at a lower voltage by forward-biasing the source-substrate junction. This approach has been investigated in detail and used to designing an ultra-low power CMOS operational amplifier for operation at ± 0.4 V. The issue of CMOS latchup and noise has been investigated in detail because of the forward biasing of the substrates of MOSFETs in CMOS. With increasing forward body-bias, the leakage current increases significantly. Dynamic threshold MOSFET (DTMOS) technique is proposed to overcome the drawback which is inherent in a forward-biased MOSFET. By using the DTMOS method with the forward source-body biased MOSFET, two low-power low-voltage CMOS VLSI circuits that of a CMOS analog multiplexer and a Schmitt trigger circuits are designed. In this dissertation, an adaptive body-bias technique is proposed. Adaptive body-bias voltage is generated for several operational frequencies. Another issue, which the chip design community is facing, is the development of portable, cost effective and low power supply voltage. This dissertation proposes a new cost-effective DC/DC converter design in standard 1.5 um n-well CMOS, which adopts a delay-line controller for voltage regulation

Development of a Sensor Readout Integrated Circuit Towards a Contact Lens for Wireless Intraocular Pressure Monitoring

This design covers the design of an integrated circuit (IC) in support of the active contact lens project at Cal Poly. The project aims to monitor intraocular eye pressure (IOP) to help diagnose and treat glaucoma, which is expected affect 6.3 million Americans by 2050. The IC is designed using IBM’s 130 nm 8RF process, is powered by an on-lens thin film 3.8 V rechargeable battery, and will be fabricated at no cost through MOSIS. The IC features a low-power linear regulator that powers a current-starved voltage-controlled oscillator (CSVCO) used for establishing a backscatter communication link. Additional circuitry is included to regulate power to and from the battery. An undervoltage lockout circuit protects the battery from deep discharge damage. When recharging, a rectifier and a voltage regulator provides overvoltage protection. These circuit blocks are biased primarily using a 696 mV subthreshold voltage reference that consumes 110.5 nA

High-Speed Low-Voltage Line Driver for SerDes Applications

The driving factor behind this research was to design & develop a line driver capable of meeting the demanding specifications of the next generation of SerDes devices. In this thesis various line driver topologies were analysed to identify a topology suited for a high-speed low-voltage operating environment. This thesis starts of by introducing a relatively new high-speed communication Device called SerDes. SerDes is used in wired chip-to-chip communications and operates by converting a parallel data stream in a serial data stream that can be then transmitted at a higher bit rate, existing SerDes devices operate up to 12.5Gbps. A matching SerDes device at the destination will then convert the serial data stream back into a parallel data stream to be read by the destination ASIC. SerDes typically uses a line driver with a differential output. Using a differential line driver increases the resilience to outside sources of noise and reduces the amount of EM radiation produced by transmission. The focus of this research is to design and develop a line driver that can operate at 40Gbps and can function with a power supply of less than IV. This demanding specification was decided to be an accurate representation of future requirements that a line driver in a SerDes device will have to conform to. A suitable line driver with a differential output was identified to meet the demanding specifications and was modified so that it can perfonn an equalisation technique called pre-distortion. Two variations of the new topology were outlined and a behavioural model was created for both using Matlab Simulink. The behavioural model for both variants proved the concept, however only one variant maintained its perfomance once the designs were implemented at transistor level in Cadence, using a 65nm CMOS technology provided by Texas Instruments. The final line driver design was then converted into a layout design, again using Cadence, and RC parasitics were extracted to perfom a post-layout simulation. The post layout simulation shows that the novel line driver can operate at 40Gbps with a power supply of 1 V - O.8V and has a power consumption of 4.54m W /Gbps. The Deterministic Jitter added by the line driver is 12.9ps

Optimization of Short-Channel RF CMOS Low Noise Amplifiers by Geometric Programming

Geometric programming (GP) is an optimization method to produce globally optimal circuit parameters with high computational efficiency. Such a method has been applied to short-channel (90 nm and 180 nm) CMOS Low Noise Amplifiers (LNAs) with common-source inductive degeneration to obtain optimal design parameters by minimizing the noise figure. An extensive survey of analytical models and experimental results reported in the literature was carried out to quantify the issue of excessive thermal noise for short-channel MOSFETs. Geometric programming compatible functions have been determined to calculate the noise figure of short-channel CMOS devices by taking into consideration channel-length modulation and velocity saturation effects

Differential Integrator Pixel Architecture for Dark Current Compensation in CMOS Image Sensors

RESUME Le Capteur d'Image CMOS (CIS) est rapidement devenu la technologie dominante dans les marchés de l'imagerie. Il y a des avantages sur les technologies avec CCD tels que la faible consommation de puissance et les faibles coûts. . La technologie CMOS APS s’est améliorée au cours des dernières décennies et propose une alternative viable à la technologie CCD pour de nombreuses applications. Néanmoins, les capteurs d’image CMOS APS ont un niveau plus élevé de courant d'obscurité que les capteurs CCD. Plusieurs techniques ont été développées pour améliorer la performance du capteur d'image en termes de courant d'obscurité qui limite sévèrement la gamme dynamique et la sensibilité des capteurs d'image. Il existe différentes approches pour réduire le courant d'obscurité. L'approche idéale, mais coûteuse, consiste à modifier le procédé de fabrication par améliorant la photosensibilité du pixel ou de réduire le courant de fuite. Cependant, certaines architectures de circuits peuvent être utilisées pour réduire ou compenser le courant d'obscurité sans modification de procédé, cette alternative fait l’objet de ce mémoire. Dans cette thèse, un circuit amplificateur différentiel multi-branche est proposé pour compenser l'effet de courant d'obscurité d’un capteurs d'image CMOS. Afin d'obtenir une application de détection à faible courant de noirceur, un interrupteur de type T avec un faible courant de fuite est utilisé. La nouvelle configuration de multiple-input multiple-output amplificateur différentiel présente l'avantage de réduire considérablement les courants d'obscurité femto-ampères des photodiodes. L'objectif étant d’améliorer la sensibilité et la gamme dynamique des pixels des capteurs d'image CMOS. Un prototype est conçu à partir du procédé de fabrication CMOS standard 0.18 µm de TSMC.----------ABSTRACT CMOS Image Sensor (CIS) rapidly became the dominant technology over Charge-Coupled-Device (CCD) in imaging markets. It has many advantages over CCDs such as low power and low cost which is highly desirable for imaging-enabled mobile devices. CMOS Active Pixel Sensor (APS) technology has improved during the last decades and suggests a viable alternative for many applications with CCD technology. Nonetheless, CMOS APS image sensors have higher dark current level than CCD sensors. Several techniques have been developed to improve the performance of image sensor in terms of dark current which severely limits the dynamic range and the sensitivity of image sensors. There are different approaches to reduce the dark current. The ideal but expensive approach is to modify the fabrication process by enhancing the photosensivity of the pixel or reducing the leakage current. However, some circuit and layout techniques reduce or compensate the dark current of standard CMOS processes which is the method considered in this work. In this thesis a multi-branch differential amplifier circuit is proposed to compensate the effect of dark current in CMOS image sensors. In order to obtain a low level sensing application, a T-type switch with low leakage current is used. The new configuration of multiple-input multiple-output differential amplifier has the advantage of compensating the femto-ampere dark currents of hotodiodes. The objective is to improve the sensitivity and the dynamic range of active pixel CMOS image sensors. A prototype is designed and simulated in a standard CMOS 0.18 µm fabrication process from TSMC

A Process Variation Tolerant Self-Compensation Sense Amplifier Design

As we move under the aegis of the Moore\u27s law, we have to deal with its darker side with problems like leakage and short channel effects. Once we go beyond 45nm regime process variations also have emerged as a significant design concern.Embedded memories uses sense amplifier for fast sensing and typically, sense amplifiers uses pair of matched transistors in a positive feedback environment. A small difference in voltage level of applied input signals to these matched transistors is amplified and the resulting logic signals are latched. Intra die variation causes mismatch between the sense transistors that should ideally be identical structures. Yield loss due to device and process variations has never been so critical to cause failure in circuits. Due to growth in size of embedded SRAMs as well as usage of sense amplifier based signaling techniques, process variations in sense amplifiers leads to significant loss of yield for that we need to come up with process variation tolerant circuit styles and new devices. In this work impact of transistor mismatch due to process variations on sense amplifier is evaluated and this problem is stated. For the solution of the problem a novel self compensation scheme on sense amplifiers is presented on different technology nodes up to 32nm on conventional bulk MOSFET technology. Our results show that the self compensation technique in the conventional bulk MOSFET latch type sense amplifier not just gives improvement in the yield but also leads to improvement in performance for latch type sense amplifiers. Lithography related CD variations, fluctuations in dopant density, oxide thickness and parametric variations of devices are identified as a major challenge to the classical bulk type MOSFET. With the emerging nanoscale devices, SIA roadmap identifies FinFETs as a candidate for post-planar end-of-roadmap CMOS device. With current technology scaling issues and with conventional bulk type MOSFET on 32nm node our technique can easily be applied to Double Gate devices. In this work, we also develop the model of Double Gate MOSFET through 3D Device Simulator Damocles and TCAD simulator. We propose a FinFET based process variation tolerant sense amplifier design that exploits the back gate of FinFET devices for dynamic compensation against process variations. Results from statistical simulation show that the proposed dynamic compensation is highly effective in restoring yield at a level comparable to that of sense amplifiers without process variations. We created the 32nm double gate models generated from Damocles 3-D device simulations [25] and Taurus Device Simulator available commercially from Synopsys [47] and use them in the nominal latch type sense amplifier design and on the Independent Gate Self Compensation Sense Amplifier Design (IGSSA) to compare the yield and performance benefits of sense amplifier design on FinFET technology over the conventional bulk type CMOS based sense amplifier on 32nm technology node effective in restoring yield at a level comparable to that of sense amplifiers without process variations. We created the 32nm double gate models generated from Damocles 3-D device simulations [25] and Taurus Device Simulator available commercially from Synopsys [47] and use them in the nominal latch type sense amplifier design and on the Independent Gate Self Compensation Sense Amplifier Design (IGSSA) to compare the yield and performance benefits of sense amplifier design on FinFET technology over the conventional bulk type CMOS based sense amplifier on 32nm technology node

Research and design of high-speed advanced analogue front-ends for fibre-optic transmission systems

In the last decade, we have witnessed the emergence of large, warehouse-scale data centres which have enabled new internet-based software applications such as cloud computing, search engines, social media, e-government etc. Such data centres consist of large collections of servers interconnected using short-reach (reach up to a few hundred meters) optical interconnect. Today, transceivers for these applications achieve up to 100Gb/s by multiplexing 10x 10Gb/s or 4x 25Gb/s channels. In the near future however, data centre operators have expressed a need for optical links which can support 400Gb/s up to 1Tb/s. The crucial challenge is to achieve this in the same footprint (same transceiver module) and with similar power consumption as today’s technology. Straightforward scaling of the currently used space or wavelength division multiplexing may be difficult to achieve: indeed a 1Tb/s transceiver would require integration of 40 VCSELs (vertical cavity surface emitting laser diode, widely used for short‐reach optical interconnect), 40 photodiodes and the electronics operating at 25Gb/s in the same module as today’s 100Gb/s transceiver. Pushing the bit rate on such links beyond today’s commercially available 100Gb/s/fibre will require new generations of VCSELs and their driver and receiver electronics. This work looks into a number of state‐of-the-art technologies and investigates their performance restraints and recommends different set of designs, specifically targeting multilevel modulation formats. Several methods to extend the bandwidth using deep submicron (65nm and 28nm) CMOS technology are explored in this work, while also maintaining a focus upon reducing power consumption and chip area. The techniques used were pre-emphasis in rising and falling edges of the signal and bandwidth extensions by inductive peaking and different local feedback techniques. These techniques have been applied to a transmitter and receiver developed for advanced modulation formats such as PAM-4 (4 level pulse amplitude modulation). Such modulation format can increase the throughput per individual channel, which helps to overcome the challenges mentioned above to realize 400Gb/s to 1Tb/s transceivers