Multiprocessor scheduling with practical constraints

The problem of scheduling tasks onto multiprocessor systems has increasing practical importance as more applications are being addressed with multiprocessor systems. Actual applications and multiprocessor systems have many characteristics which become constraints to the general scheduling problem of minimizing the schedule length. These practical constraints include precedence relations and communication delays between tasks, yet few researchers have considered both these constraints when developing schedulers. This work examines a more general multiprocessor scheduling problem, which includes these practical scheduling constraints, and develops a new scheduling heuristic using a list scheduler with dynamically computed priorities. The dynamic priority heuristic is compared against an optimal scheduler and against other researchers’ approaches for thousands of randomly generated scheduling problems. The dynamic priority heuristic produces schedules with lengths which are 10% to 20% over optimal on the average. The dynamic priority heuristic performs better than other researchers’ approaches for scheduling problems with the practical constraints. We conclude that it is important to consider practical constraints in the design of a scheduler and that a simple heuristic can still achieve good performance in this area

Joint Routing and STDMA-based Scheduling to Minimize Delays in Grid Wireless Sensor Networks

In this report, we study the issue of delay optimization and energy efficiency in grid wireless sensor networks (WSNs). We focus on STDMA (Spatial Reuse TDMA)) scheduling, where a predefined cycle is repeated, and where each node has fixed transmission opportunities during specific slots (defined by colors). We assume a STDMA algorithm that takes advantage of the regularity of grid topology to also provide a spatially periodic coloring ("tiling" of the same color pattern). In this setting, the key challenges are: 1) minimizing the average routing delay by ordering the slots in the cycle 2) being energy efficient. Our work follows two directions: first, the baseline performance is evaluated when nothing specific is done and the colors are randomly ordered in the STDMA cycle. Then, we propose a solution, ORCHID that deliberately constructs an efficient STDMA schedule. It proceeds in two steps. In the first step, ORCHID starts form a colored grid and builds a hierarchical routing based on these colors. In the second step, ORCHID builds a color ordering, by considering jointly both routing and scheduling so as to ensure that any node will reach a sink in a single STDMA cycle. We study the performance of these solutions by means of simulations and modeling. Results show the excellent performance of ORCHID in terms of delays and energy compared to a shortest path routing that uses the delay as a heuristic. We also present the adaptation of ORCHID to general networks under the SINR interference model

Simulation and experimental evaluation of a flexible time triggered ethernet architecture applied in satellite nano/micro launchers

The success of small satellites has led to the study of new technologies for the realization of Nano and Micro Launch Vehicle (NMLV) in order to make competitive launch costs. The paper has the objective to define and experimentally investigate the performance of a communication system for NMLV interconnecting the End Systems as On-Board Computer (OBC), telemetry apparatus, Navigation Unit...we propose a low cost Ethernet-based solution able to provide the devices with high interconnection bandwidth. To guarantee hard delays to the Guide, Navigation and Control applications we propose some architectural changes of the traditional Ethernet network with the introduction of a layer implemented in the End Systems and allow for the lack of any contention on the network links. We show how the proposed solution has comparable performance to the one of TTEthernet standard that is a very expensive solution. An experimental test-bed equipped with Ethernet switches and Hercules boards by Texas Instruments is also provided to prove the feasibility of the proposed solution