Algorithms and Circuits for Analog-Digital Hybrid Multibeam Arrays

Fifth generation (5G) and beyond wireless communication systems will rely heavily on larger antenna arrays combined with beamforming to mitigate the high free-space path-loss that prevails in millimeter-wave (mmW) and above frequencies. Sharp beams that can support wide bandwidths are desired both at the transmitter and the receiver to leverage the glut of bandwidth available at these frequency bands. Further, multiple simultaneous sharp beams are imperative for such systems to exploit mmW/sub-THz wireless channels using multiple reflected paths simultaneously. Therefore, multibeam antenna arrays that can support wider bandwidths are a key enabler for 5G and beyond systems. In general, N-beam systems using N-element antenna arrays will involve circuit complexities of the order of N2. This dissertation investigates new analog, digital and hybrid low complexity multibeam beamforming algorithms and circuits for reducing the associated high size, weight, and power (SWaP) complexities in larger multibeam arrays. The research efforts on the digital beamforming aspect propose the use of a new class of discrete Fourier transform (DFT) approximations for multibeam generation to eliminate the need for digital multipliers in the beamforming circuitry. For this, 8-, 16- and 32-beam multiplierless multibeam algorithms have been proposed for uniform linear array applications. A 2.4 GHz 16-element array receiver setup and a 5.8 GHz 32-element array receiver system which use field programmable gate arrays (FPGAs) as digital backend have been built for real-time experimental verification of the digital multiplierless algorithms. The multiplierless algorithms have been experimentally verified by digitally measuring beams. It has been shown that the measured beams from the multiplierless algorithms are in good agreement with the exact counterpart algorithms. Analog realizations of the proposed approximate DFT transforms have also been investigated leading to low-complex, high bandwidth circuits in CMOS. Further, a novel approach for reducing the circuit complexity of analog true-time delay (TTD) N-beam beamforming networks using N-element arrays has been proposed for wideband squint-free operation. A sparse factorization of the N-beam delay Vandermonde beamforming matrix is used to reduce the total amount of TTD elements that are needed for obtaining N number of beams in a wideband array. The method has been verified using measured responses of CMOS all-pass filters (APFs). The wideband squint-free multibeam algorithm is also used to propose a new low-complexity hybrid beamforming architecture targeting future 5G mmW systems. Apart from that, the dissertation also explores multibeam beamforming architectures for uniform circular arrays (UCAs). An algorithm having N log N circuit complexity for simultaneous generation of N-beams in an N-element UCA is explored and verified

Optimization Algorithms For The Multiple Constant Multiplications Problem

(Doktora) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2009(PhD) -- İstanbul Technical University, Institute of Science and Technology, 2009Bu tezde, birden fazla katsayının çarpımı (MCM) problemi, bir başka deyişle, bir değişkenin birden fazla katsayı ile çarpımının minimum sayıda toplama/çıkarma işlemi kullanılarak gerçeklenmesi için tasarlanmış kesin ve yaklaşık algoritmalar sunulmaktadır. Bir kesin alt ifade eliminasyonu (CSE) algoritmasının tasarımında, MCM problemini bir 0-1 tamsayı lineer programlama problemi olarak modelleyen daha önceden önerilmiş bir algoritma temel alınmıştır. Kesin CSE algoritması içinde, alan ve gecikme ölçütlerini ele alabilmek için yeni bir kesin model önerilmektedir. Kesin CSE algoritması tarafından taranacak arama uzayını küçültmek için problem indirgeme ve model basitleştirme teknikleri sunulmaktadır. Bu tekniklerin kullanımının kesin CSE algoritmasının daha büyük örnekler üzerinde uygulanmasına olanak sağladığı gösterilmektedir. Ayrıca, bu teknikler ile donatılmış kesin CSE algoritması, katsayıları genel sayı gösteriminde ele alacak ve kesin CSE algoritmasından daha iyi sonuçlar elde edecek şekilde genişletilmektedir. Bunların yanında, gerçek boyutlu örnekler üzerinde uygulanabilen bir kesin graf tabanlı algoritma sunulmaktadır. Bu kesin algoritmalara ek olarak, minimum sonuçlara oldukça yakın çözümler bulabilen ve kesin algoritmaların ele almakta zorlandığı örneklere uygulanabilen yaklaşık CSE ve graf tabanlı algoritmalar verilmektedir. Bu tezde önerilen kesin ve yaklaşık algoritmaların daha önceden önerilmiş sezgisel yöntemlerden daha iyi sonuçlar verdiği gösterilmektedir. Bunların yanısıra, bu tezde, kesin CSE algoritması gecikme kısıtı altında alanın minimize edilmesi, kapı seviyesinde alanın minimize edilmesi ve yüksek hızlı sayısal sonlu impuls cevaplı filtrelerin tasarımında alanın optimize edilmesi problemlerine uygulanmaktadır.In this thesis, exact and approximate algorithms designed for the multiple constant multiplications (MCM) problem, i.e., the implementation of the multiplication of a variable with multiple constants using minimum number of addition/subtraction operations, are introduced. In the design of an exact common subexpression elimination (CSE) algorithm, we relied on the previously proposed algorithm that models the MCM problem as a 0-1 integer linear programming problem. To handle the area and delay parameters in the exact CSE algorithm, a new exact model is proposed. To reduce the search space to be explored by the exact algorithm, problem reduction and model simplification techniques are introduced. It is shown that the use of these techniques enable the exact CSE algorithm to be applied on larger size instances. Also, the exact CSE algorithm equipped with these techniques is extended to handle the constants under general number representation yielding better solutions than those of the exact CSE algorithm. Besides, an exact graph-based algorithm that can be applied on real size instances is introduced. In addition to the exact algorithms, approximate CSE and graph-based algorithms that find similar results with the minimum solutions and can be applied on instances that the exact algorithms cannot deal with are presented. It is shown that the exact and approximate algorithms proposed in this thesis give better solutions than those of the previously proposed heuristic algorithms. Furthermore, in this thesis, the exact CSE algorithm is applied on the minimization of area under a delay constraint, the minimization of area at gate-level, and the optimization of area in high-speed digital finite impulse response filters synthesis problems.DoktoraPh

Multirate digital filters, filter banks, polyphase networks, and applications: a tutorial

Multirate digital filters and filter banks find application in communications, speech processing, image compression, antenna systems, analog voice privacy systems, and in the digital audio industry. During the last several years there has been substantial progress in multirate system research. This includes design of decimation and interpolation filters, analysis/synthesis filter banks (also called quadrature mirror filters, or QMFJ, and the development of new sampling theorems. First, the basic concepts and building blocks in multirate digital signal processing (DSPJ, including the digital polyphase representation, are reviewed. Next, recent progress as reported by several authors in this area is discussed. Several applications are described, including the following: subband coding of waveforms, voice privacy systems, integral and fractional sampling rate conversion (such as in digital audio), digital crossover networks, and multirate coding of narrow-band filter coefficients. The M-band QMF bank is discussed in considerable detail, including an analysis of various errors and imperfections. Recent techniques for perfect signal reconstruction in such systems are reviewed. The connection between QMF banks and other related topics, such as block digital filtering and periodically time-varying systems, based on a pseudo-circulant matrix framework, is covered. Unconventional applications of the polyphase concept are discussed

Circuit paradigm in the 21

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Project and development of hardware accelerators for fast computing in multimedia processing

2017 - 2018The main aim of the present research work is to project and develop very large scale electronic integrated circuits, with particular attention to the ones devoted to image processing applications and the related topics. In particular, the candidate has mainly investigated four topics, detailed in the following. First, the candidate has developed a novel multiplier circuit capable of obtaining floating point (FP32) results, given as inputs an integer value from a fixed integer range and a set of fixed point (FI) values. The result has been accomplished exploiting a series of theorems and results on a number theory problem, known as Bachet’s problem, which allows the development of a new Distributed Arithmetic (DA) based on 3’s partitions. This kind of application results very fit for filtering applications working on an integer fixed input range, such in image processing applications, in which the pixels are coded on 8 bits per channel. In fact, in these applications the main problem is related to the high area and power consumption due to the presence of many Multiply and Accumulate (MAC) units, also compromising real-time requirements due to the complexity of FP32 operations. For these reasons, FI implementations are usually preferred, at the cost of lower accuracies. The results for the single multiplier and for a filter of dimensions 3x3 show respectively delay of 2.456 ns and 4.7 ns on FPGA platform and 2.18 ns and 4.426 ns on 90nm std_cell TSMC 90 nm implementation. Comparisons with state-of-the-art FP32 multipliers show a speed increase of up to 94.7% and an area reduction of 69.3% on FPGA platform. ... [edited by Author]XXXI cicl

Survey of FPGA applications in the period 2000 – 2015 (Technical Report)

Romoth J, Porrmann M, Rückert U. Survey of FPGA applications in the period 2000 – 2015 (Technical Report).; 2017.Since their introduction, FPGAs can be seen in more and more different fields of applications. The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware. Nevertheless, every application field introduces special requirements to the used computational architecture. This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs

Systolic Array Implementations With Reduced Compute Time.

The goal of the research is the establishment of a formal methodology to develop computational structures more suitable for the changing nature of real-time signal processing and control applications. A major effort is devoted to the following question: Given a systolic array designed to execute a particular algorithm, what other algorithms can be executed on the same array? One approach for answering this question is based on a general model of array operations using graph-theoretic techniques. As a result, a systematic procedure is introduced that models array operations as a function of the compute cycle. As a consequence of the analysis, the dissertation develops the concept of fast algorithm realizations. This concept characterizes specific realizations that can be evaluated in a reduced number of cycles. It restricts the operations to remain in the same class but with reduced execution time. The concept takes advantage of the data dependencies of the algorithm at hand. This feature allows the modification of existing structures by reordering the input data. Applications of the principle allows optimum time band and triangular matrix product on arrays designed for dense matrices. A second approach for analyzing the families of algorithms implementable in an array, is based on the concept of array time constrained operation. The principle uses the number of compute cycle as an additional degree of freedom to expand the class of transformations generated by a single array. A mathematical approach, based on concepts from multilinear algebra, is introduced to model the recursive transformations implemented in linear arrays at each compute cycle. The proposed representation is general enough to encompass a large class of signal processing and control applications. A complete analytical model of the linear maps implementable by the array at each compute cycle is developed. The proposed methodology results in arrays that are more adaptable to the changing nature of operations. Lessons learned from analyzing existing arrays are used to design smart arrays for special algorithm realizations. Applications of the methodology include the design of flexible time structures and the ability to decompose a full size array into subarrays implementing smaller size problems

Waveform Design for 5G and beyond Systems

5G traffic has very diverse requirements with respect to data rate, delay, and reliability. The concept of using multiple OFDM numerologies adopted in the 5G NR standard will likely meet these multiple requirements to some extent. However, the traffic is radically accruing different characteristics and requirements when compared with the initial stage of 5G, which focused mainly on high-speed multimedia data applications. For instance, applications such as vehicular communications and robotics control require a highly reliable and ultra-low delay. In addition, various emerging M2M applications have sparse traffic with a small amount of data to be delivered. The state-of-the-art OFDM technique has some limitations when addressing the aforementioned requirements at the same time. Meanwhile, numerous waveform alternatives, such as FBMC, GFDM, and UFMC, have been explored. They also have their own pros and cons due to their intrinsic waveform properties. Hence, it is the opportune moment to come up with modification/variations/combinations to the aforementioned techniques or a new waveform design for 5G systems and beyond. The aim of this Special Issue is to provide the latest research and advances in the field of waveform design for 5G systems and beyond

Design and analysis of short word length DSP systems for mobile communication

Recently, many general purpose DSP applications such as Least Mean Squares-Like single-bit adaptive filter algorithms have been developed using the Short Word Length (SWL) technique and have been shown to achieve similar performance as multi-bit systems. A key function in SWL systems is sigma delta modulation (ΣΔM) that operates at an over sampling ratio (OSR), in contrast to the Nyquist rate sampling typically used in conventional multi-bit systems. To date, the analysis of SWL (or single-bit) DSP systems has tended to be performed using high-level tools such as MATLAB, with little work reported relating to their hardware implementation, particularly in Field Programmable Gate Arrays (FPGAs). This thesis explores the hardware implementation of single-bit systems in FPGA using the design and implementation in VHDL of a single-bit ternary FIR-like filter as an illustrative example. The impact of varying OSR and bit-width of the SWL filter has been determined, and a comparison undertaken between the area-performance-power characteristics of the SWL FIR filter compared to its equivalent multi-bit filter. In these experiments, it was found that single-bit FIR-like filter consistently outperforms the multi-bit technique in terms of its area, performance and power except at the highest filter orders analysed in this work. At higher orders, the ΣΔ approach retains its power and performance advantages but exhibits slightly higher chip area. In the second stage of thesis, three encoding techniques called canonical signed digit (CSD), 2’s complement, and Redundant Binary Signed Digit (RBSD) were designed and investigated on the basis of area-performance in FPGA at varying OSR. Simulation results show that CSD encoding technique does not offer any significant improvement as compared to 2’s complement as in multi-bit domain. Whereas, RBSD occupies double the chip area than other two techniques and has poor performance. The stability of the single-bit FIR-like filter mainly depends upon IIR remodulator due to its recursive nature. Thus, we have investigated the stability IIR remodulator and propose a new model using linear analysis and root locus approach that takes into account the widely accepted second order sigma-delta modulator state variable upper bounds. Using proposed model we have found new feedback parameters limits that is a key parameter in single-bit IIR remodulator stability analysis. Further, an analysis of single-bit adaptive channel equalization in MATLAB has been performed, which is intended to support the design and development of efficient algorithm for single-bit channel equalization. A new mathematical model has been derived with all inputs, coefficients and outputs in single-bit domain. The model was simulated using narrowband signals in MATLAB and investigated on the basis of symbol error rate (SER), signal-to-noise ratio (SNR) and minimum mean squared error (MMSE). The results indicate that single-bit adaptive channel equalization is achievable with narrowband signals but that the harsh quantization noise has great impact in the convergence