Implementation of a Symbolic Circuit Simulator for Topological Network Analysis

Abstract- Many topological approaches to symbolic network analysis have been proposed in the literature, but none are implemented ultimately as a simulator for large network analysis due to their complexity and exponentially increasing number of terms. A novel methodology adopted in this paper uses a graph reduction approach based on a set of graph reduction rules developed recently. Furthermore, a Binary Decision Diagram is used in the implementation of a symbolic simulator that is capable of analyzing large analog circuit blocks. Implementation details and experimental results are reported. Keywords-admissible term, BDD, graph reduction, symbolic analysis I

An error-controlled methodology for approximate hierarchical symbolic analysis

Limitations of existing approaches for symbolic analysis of large analog circuits are discussed. To address their solution, a new methodology for hierarchical symbolic analysis is introduced. The combination of a hierarchical modeling technique and approximation strategies, comprising circuit reduction, graph-based symbolic solution of circuit equations and matrix-based error control, provides optimum results in terms of speech and quality of results.European Commission ESPRIT 21812Comisión Interministerial de Ciencia y Tecnología TIC97-058

Hierarchical gate-level verification of speed-independent circuits

This paper presents a method for the verification of speed-independent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on the number of state signals (C elements, RS flip-flops) of the circuit. Despite the reduction to complex gates, verification is kept exact. The specification of the environment only requires to describe the transitions of the input/output signals of the circuit and is allowed to express choice and non-determinism. Experimental results obtained from circuits with more than 500 gates show that the computational cost can be drastically reduced when using hierarchical verification.Peer ReviewedPostprint (published version

Comparison of matroid intersection algorithms for large circuit analysis

This paper presents two approaches to symbolic analysis of large analog integrated circuits via simplification during the generation of the symbolic expressions. Both techniques are examined from the point of view of matroid theory. Finally, a new approach which combines the positive features of both approaches is introduced

Error control in simplification before generation algorithms for symbolic analysis of large analogue circuits

Circuit reduction is a fundamental first step in addressing the symbolic analysis of large analogue circuits. A new algorithm for simplification before generation is presented which is very efficient in terms of speed and the amount of circuit reduction, and solves the accuracy problems of previously reported approaches

An advanced symbolic analyzer for the automatic generation of analog circuit design equations

A tool for symbolic analysis of analog integrated circuits is presented featuring accurate simplification, pole/zero extraction, and tools for parametric AC circuit characterization. The program, called ASAP, uses signal flowgraph methods and has been written in C for portability. In its current version, ASAP is able to deal with the complexity levels arising in typical analog building blocks when described by device-level models. The ASAP inputs and outputs, the architecture, and the graphical interface are discussed

Symbolic analysis tools-the state of the art

This paper reviews the main last generation symbolic analyzers, comparing them in terms of functionality, pointing out also their shortcomings. The state of the art in this field is also studied, pointing out directions for future research

Index Reduction for Differential-Algebraic Equations with Mixed Matrices

Differential-algebraic equations (DAEs) are widely used for modeling of dynamical systems. The difficulty in solving numerically a DAE is measured by its differentiation index. For highly accurate simulation of dynamical systems, it is important to convert high-index DAEs into low-index DAEs. Most of existing simulation software packages for dynamical systems are equipped with an index-reduction algorithm given by Mattsson and S\"{o}derlind. Unfortunately, this algorithm fails if there are numerical cancellations. These numerical cancellations are often caused by accurate constants in structural equations. Distinguishing those accurate constants from generic parameters that represent physical quantities, Murota and Iri introduced the notion of a mixed matrix as a mathematical tool for faithful model description in structural approach to systems analysis. For DAEs described with the use of mixed matrices, efficient algorithms to compute the index have been developed by exploiting matroid theory. This paper presents an index-reduction algorithm for linear DAEs whose coefficient matrices are mixed matrices, i.e., linear DAEs containing physical quantities as parameters. Our algorithm detects numerical cancellations between accurate constants, and transforms a DAE into an equivalent DAE to which Mattsson--S\"{o}derlind's index-reduction algorithm is applicable. Our algorithm is based on the combinatorial relaxation approach, which is a framework to solve a linear algebraic problem by iteratively relaxing it into an efficiently solvable combinatorial optimization problem. The algorithm does not rely on symbolic manipulations but on fast combinatorial algorithms on graphs and matroids. Furthermore, we provide an improved algorithm under an assumption based on dimensional analysis of dynamical systems.Comment: A preliminary version of this paper is to appear in Proceedings of the Eighth SIAM Workshop on Combinatorial Scientific Computing, Bergen, Norway, June 201