258 research outputs found
Doctor of Philosophy
dissertationPortable electronic devices will be limited to available energy of existing battery chemistries for the foreseeable future. However, system-on-chips (SoCs) used in these devices are under a demand to offer more functionality and increased battery life. A difficult problem in SoC design is providing energy-efficient communication between its components while maintaining the required performance. This dissertation introduces a novel energy-efficient network-on-chip (NoC) communication architecture. A NoC is used within complex SoCs due it its superior performance, energy usage, modularity, and scalability over traditional bus and point-to-point methods of connecting SoC components. This is the first academic research that combines asynchronous NoC circuits, a focus on energy-efficient design, and a software framework to customize a NoC for a particular SoC. Its key contribution is demonstrating that a simple, asynchronous NoC concept is a good match for low-power devices, and is a fruitful area for additional investigation. The proposed NoC is energy-efficient in several ways: simple switch and arbitration logic, low port radix, latch-based router buffering, a topology with the minimum number of 3-port routers, and the asynchronous advantages of zero dynamic power consumption while idle and the lack of a clock tree. The tool framework developed for this work uses novel methods to optimize the topology and router oorplan based on simulated annealing and force-directed movement. It studies link pipelining techniques that yield improved throughput in an energy-efficient manner. A simulator is automatically generated for each customized NoC, and its traffic generators use a self-similar message distribution, as opposed to Poisson, to better match application behavior. Compared to a conventional synchronous NoC, this design is superior by achieving comparable message latency with half the energy
Resource optimization for fault-tolerant quantum computing
In this thesis we examine a variety of techniques for reducing the resources
required for fault-tolerant quantum computation. First, we show how to simplify
universal encoded computation by using only transversal gates and standard
error correction procedures, circumventing existing no-go theorems. We then
show how to simplify ancilla preparation, reducing the cost of error correction
by more than a factor of four. Using this optimized ancilla preparation, we
develop improved techniques for proving rigorous lower bounds on the noise
threshold.
Additional overhead can be incurred because quantum algorithms must be
translated into sequences of gates that are actually available in the quantum
computer. In particular, arbitrary single-qubit rotations must be decomposed
into a discrete set of fault-tolerant gates. We find that by using a special
class of non-deterministic circuits, the cost of decomposition can be reduced
by as much as a factor of four over state-of-the-art techniques, which
typically use deterministic circuits.
Finally, we examine global optimization of fault-tolerant quantum circuits
under physical connectivity constraints. We adapt techniques from VLSI in order
to minimize time and space usage for computations in the surface code, and we
develop a software prototype to demonstrate the potential savings.Comment: 231 pages, Ph.D. thesis, University of Waterlo
New Logic Synthesis As Nanotechnology Enabler (invited paper)
Nanoelectronics comprises a variety of devices whose electrical properties are more complex as compared to CMOS, thus enabling new computational paradigms. The potentially large space for innovation has to be explored in the search for technologies that can support large-scale and high- performance circuit design. Within this space, we analyze a set of emerging technologies characterized by a similar computational abstraction at the design level, i.e., a binary comparator or a majority voter. We demonstrate that new logic synthesis techniques, natively supporting this abstraction, are the technology enablers. We describe models and data-structures for logic design using emerging technologies and we show results of applying new synthesis algorithms and tools. We conclude that new logic synthesis methods are required to both evaluate emerging technologies and to achieve the best results in terms of area, power and performance
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