189 research outputs found

    A general analytical model of adaptive wormhole routing in k-ary n-cubes

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    Several analytical models of fully adaptive routing have recently been proposed for k-ary n-cubes and hypercube networks under the uniform traffic pattern. Although,hypercube is a special case of k-ary n-cubes topology, the modeling approach for hypercube is more accurate than karyn-cubes due to its simpler structure. This paper proposes a general analytical model to predict message latency in wormhole-routed k-ary n-cubes with fully adaptive routing that uses a similar modeling approach to hypercube. The analysis focuses Duato's fully adaptive routing algorithm [12], which is widely accepted as the most general algorithm for achieving adaptivity in wormhole-routed networks while allowing for an efficient router implementation. The proposed model is general enough that it can be used for hypercube and other fully adaptive routing algorithms

    Adaptive turn-prohibition routing algorithm for the networks of workstations

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    Deadlock occurrence is a critical problem for any computer network. Various solutions have been proposed over last two decades to solve problem of deadlocks in networks using different routing schemes, like up/down routing algorithm used in Myrinet switches. However, most of existing approaches for deadlock-free routing either try to eliminate any possibility of deadlock occurrence, which can result in putting extra restrictions on the routing in the networks or put no restrictions on routing, which leads to other approach namely deadlock recovery. In this thesis emphasis is on developing hybrid approach for routing in wormhole networks, wherein some prohibition is imposed on routing along with some kind of deadlock recovery. This adaptive approach allows changing the amount of routing restrictions depending on network traffic, thus providing a flexible method to achieve better network performance compared to the existing techniques. The main idea of the proposed method consists in the sequential selections of some turns, which are prohibited to be selected during routing. After each additional turn is added, the probability of deadlock occurrence decreases gradually. Cost formula is proposed to estimate cost of implementing both strategies in a network which is basis of proposed adaptive model

    OutFlank Routing: Increasing Throughput in Toroidal Interconnection Networks

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    We present a new, deadlock-free, routing scheme for toroidal interconnection networks, called OutFlank Routing (OFR). OFR is an adaptive strategy which exploits non-minimal links, both in the source and in the destination nodes. When minimal links are congested, OFR deroutes packets to carefully chosen intermediate destinations, in order to obtain travel paths which are only an additive constant longer than the shortest ones. Since routing performance is very sensitive to changes in the traffic model or in the router parameters, an accurate discrete-event simulator of the toroidal network has been developed to empirically validate OFR, by comparing it against other relevant routing strategies, over a range of typical real-world traffic patterns. On the 16x16x16 (4096 nodes) simulated network OFR exhibits improvements of the maximum sustained throughput between 14% and 114%, with respect to Adaptive Bubble Routing.Comment: 9 pages, 5 figures, to be presented at ICPADS 201

    An Efficient Routing Implementation for Irregular Networks

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    with the recent advancements in multi-core era workstation clusters have emerged as a cost-effective approach to build a network of workstations NOWs NOWs connect the small groups of processors to a network of switching elements that form irregular topologies Designing an efficient routing and a deadlock avoidance algorithm for irregular networks is quite complicated in terms of latency and area of the routing tables thus impractical for scalability of On Chip Networks Many deadlock free routing mechanisms have been proposed for regular networks but they cannot be employed in irregular networks In this paper a new methodology has been proposed for efficient routing scheme called LBDR-UD which save the average 64 59 routing tables in the switch for irregular networks as compare to up down routing The Basic concept of routing scheme is combination of up down and Logic Based Distributed Routing By simulation it has been shown that the LBDR-UD is deadlock free and adaptive to all dynamic network traffic condition

    The impacts of timing constraints on virtual channels multiplexing in interconnect networks

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    Interconnect networks employing wormhole-switching play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs, multicomputer systems and system area networks. Virtual channels greatly improve the performance of wormhole-switched networks because they reduce blocking by acting as "bypass" lanes for non-blocked messages. Capturing the effects of virtual channel multiplexing has always been a crucial issue for any analytical model proposed for wormhole-switched networks. Dally has developed a model to investigate the behaviour of this multiplexing which have been widely employed in the subsequent analytical models of most routing algorithms suggested in the literature. It is indispensable to modify Dally's model in order to evaluate the performance of channel multiplexing in more general networks where restrictions such as timing constraints of input arrivals and finite buffer size of queues are common. In this paper we consider timing constraints of input arrivals to investigate the virtual channel multiplexing problem inherent in most current networks. The analysis that we propose is completely general and therefore can be used with any interconnect networks employing virtual channels. The validity of the proposed equations has been verified through simulation experiments under different working conditions

    Quarc: an architecture for efficient on-chip communication

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    The exponential downscaling of the feature size has enforced a paradigm shift from computation-based design to communication-based design in system on chip development. Buses, the traditional communication architecture in systems on chip, are incapable of addressing the increasing bandwidth requirements of future large systems. Networks on chip have emerged as an interconnection architecture offering unique solutions to the technological and design issues related to communication in future systems on chip. The transition from buses as a shared medium to networks on chip as a segmented medium has given rise to new challenges in system on chip realm. By leveraging the shared nature of the communication medium, buses have been highly efficient in delivering multicast communication. The segmented nature of networks, however, inhibits the multicast messages to be delivered as efficiently by networks on chip. Relying on extensive research on multicast communication in parallel computers, several network on chip architectures have offered mechanisms to perform the operation, while conforming to resource constraints of the network on chip paradigm. Multicast communication in majority of these networks on chip is implemented by establishing a connection between source and all multicast destinations before the message transmission commences. Establishing the connections incurs an overhead and, therefore, is not desirable; in particular in latency sensitive services such as cache coherence. To address high performance multicast communication, this research presents Quarc, a novel network on chip architecture. The Quarc architecture targets an area-efficient, low power, high performance implementation. The thesis covers a detailed representation of the building blocks of the architecture, including topology, router and network interface. The cost and performance comparison of the Quarc architecture against other network on chip architectures reveals that the Quarc architecture is a highly efficient architecture. Moreover, the thesis introduces novel performance models of complex traffic patterns, including multicast and quality of service-aware communication
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