Measurements, Models, Systems and Design

531 s.

Vector processing-aware advanced clock-gating techniques for low-power fused multiply-add

The need for power efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a retailoring for the mobile market that they are entering now. Floating-point (FP) fused multiply-add (FMA), being a functional unit with high power consumption, deserves special attention. Although clock gating is a well-known method to reduce switching power in synchronous designs, there are unexplored opportunities for its application to vector processors, especially when considering active operating mode. In this research, we comprehensively identify, propose, and evaluate the most suitable clock-gating techniques for vector FMA units (VFUs). These techniques ensure power savings without jeopardizing the timing. We evaluate the proposed techniques using both synthetic and “real-world” application-based benchmarking. Using vector masking and vector multilane-aware clock gating, we report power reductions of up to 52%, assuming active VFU operating at the peak performance. Among other findings, we observe that vector instruction-based clock-gating techniques achieve power savings for all vector FP instructions. Finally, when evaluating all techniques together, using “real-world” benchmarking, the power reductions are up to 80%. Additionally, in accordance with processor design trends, we perform this research in a fully parameterizable and automated fashion.The research leading to these results has received funding from the RoMoL ERC Advanced Grant GA 321253 and is supported in part by the European Union (FEDER funds) under contract TTIN2015-65316-P. The work of I. Ratkovic was supported by a FPU research grant from the Spanish MECD.Peer ReviewedPostprint (author's final draft

Comparison of different design alternatives for hardware-in-the-loop of power converters

This paper aims to compare different design alternatives of hardware-in-the-loop (HIL) for emulating power converters in Field Programmable Gate Arrays (FPGAs). It proposes various numerical formats (fixed and floating-point) and different approaches (pure VHSIC Hardware Description Language (VHDL), Intellectual Properties (IPs), automated MATLAB HDL code, and High-Level Synthesis (HLS)) to design power converters. Although the proposed models are simple power electronics HIL systems, the idea can be extended to any HIL system. This study compares the design effort of different coding methods and numerical formats considering possible synthesis tools (Precision and Vivado), and it comprises an analytical discussion in terms of area and speed. The different models are synthesized as ad-hoc modules in general-purpose FPGAs, but also using the NI myRIO device as an example of a commercial tool capable of implementing HIL models. The comparison confirms that the optimum design alternative must be chosen based on the application (complexity, frequency, etc.) and designers’ constraints, such as available area, coding expertise, and design effor

The Expanded Very Large Array

In almost 30 years of operation, the Very Large Array (VLA) has proved to be a remarkably flexible and productive radio telescope. However, the basic capabilities of the VLA have changed little since it was designed. A major expansion utilizing modern technology is currently underway to improve the capabilities of the VLA by at least an order of magnitude in both sensitivity and in frequency coverage. The primary elements of the Expanded Very Large Array (EVLA) project include new or upgraded receivers for continuous frequency coverage from 1 to 50 GHz, new local oscillator, intermediate frequency, and wide bandwidth data transmission systems to carry signals with 16 GHz total bandwidth from each antenna, and a new digital correlator with the capability to process this bandwidth with an unprecedented number of frequency channels for an imaging array. Also included are a new monitor and control system and new software that will provide telescope ease of use. Scheduled for completion in 2012, the EVLA will provide the world research community with a flexible, powerful, general-purpose telescope to address current and future astronomical issues.Comment: Added journal reference: published in Proceedings of the IEEE, Special Issue on Advances in Radio Astronomy, August 2009, vol. 97, No. 8, 1448-1462 Six figures, one tabl

Realising intelligent virtual design

This paper presents a vision and focus for the CAD Centre research: the Intelligent Design Assistant (IDA). The vision is based upon the assumption that the human and computer can operate symbiotically, with the computer providing support for the human within the design process. Recently however the focus has been towards the development of integrated design platforms that provide general support irrespective of the domain, to a number of distributed collaborative designers. This is illustrated within the successfully completed Virtual Reality Ship (VRS) virtual platform, and the challenges are discussed further within the NECTISE, SAFEDOR and VIRTUE projects

Realising intelligent virtual design

This paper presents a vision and focus for the CAD Centre research: the Intelligent Design Assistant (IDA). The vision is based upon the assumption that the human and computer can operate symbiotically, with the computer providing support for the human within the design process. Recently however the focus has been towards the development of integrated design platforms that provide general support irrespective of the domain, to a number of distributed collaborative designers. This is illustrated within the successfully completed Virtual Reality Ship (VRS) virtual platform, and the challenges are discussed further within the NECTISE, SAFEDOR and VIRTUE projects

Digital implementation of the cellular sensor-computers

Two different kinds of cellular sensor-processor architectures are used nowadays in various applications. The first is the traditional sensor-processor architecture, where the sensor and the processor arrays are mapped into each other. The second is the foveal architecture, in which a small active fovea is navigating in a large sensor array. This second architecture is introduced and compared here. Both of these architectures can be implemented with analog and digital processor arrays. The efficiency of the different implementation types, depending on the used CMOS technology, is analyzed. It turned out, that the finer the technology is, the better to use digital implementation rather than analog