A Four-Transistor Level Converter for Dual-Voltage Low-Power Design

Power dissipation in digital circuits has become a primary concern in electronic design. With increasing usage of portable devices, there are severe restrictions being placed on the size, weight and power of batteries. In this work, we propose a design of a dual V th feedback type four-transistor level converter (DVF4) with reduced delay and power overheads. The use of DVF4 enhances the effectiveness of a dual-voltage low-power design. The level converter can be used in a circuit with multi supply voltage system where low supply gates may feed into high supply gates resulting in lower power and higher speed than with previously published level converters. The proposed level converter is based on a feedback circuit and employs multi-V th technique. To portray the advantages, we compare the proposed level converter with a previously published level converter for various supply voltages and observe 17.44% to 53% power savings and around 50% delay reduction over the best 32 nm CMOS design available in the literature. The impact of process variations is also examined. When used with dual VDD designs, the new level converter renders up to 61% more energy savings for benchmark circuits in comparison when level converters are not allowed. Furthermore, a level converter flip-flop combination performs better than an existing level converting flip-flop. A single-threshold alternative of the new level converter still remains effective, though over a reduced voltage range

Asynchronous Circuit Stacking for Simplified Power Management

As digital integrated circuits (ICs) continue to increase in complexity, new challenges arise for designers. Complex ICs are often designed by incorporating multiple power domains therefore requiring multiple voltage converters to produce the corresponding supply voltages. These converters not only take substantial on-chip layout area and/or off-chip space, but also aggregate the power loss during the voltage conversions that must occur fast enough to maintain the necessary power supplies. This dissertation work presents an asynchronous Multi-Threshold NULL Convention Logic (MTNCL) “stacked” circuit architecture that alleviates this problem by reducing the number of voltage converters needed to supply the voltage the ICs operate at. By stacking multiple MTNCL circuits between power and ground, supplying a multiple of VDD to the entire stack and incorporating simple control mechanisms, the dynamic range fluctuation problem can be mitigated. A 130nm Bulk CMOS process and a 32nm Silicon-on-Insulator (SOI) CMOS process are used to evaluate the theoretical effect of stacking different circuitry while running different workloads. Post parasitic physical implementations are then carried out in the 32nm SOI process for demonstrating the feasibility and analyzing the advantages of the proposed MTNCL stacking architecture

Switched Capacitor DC-DC Converter for Miniaturised Wearable Systems

Motivated by the demands of the integrated power system in the modern wearable electronics, this paper presents a new method of inductor-less switched-capacitor (SC) based DC-DC converter designed to produce two simultaneous boost and buck outputs by using a 4-phases logic switch mode regulation. While the existing SC converters missing their reconfigurability during needed spontaneous multi-outputs at the load ends, this work overcomes this limitation by being able to reconfigure higher gain mode at dual outputs. From an input voltage of 2.5 V, the proposed converter achieves step-up and step-down voltage conversions of 3.74 V and 1.233 V for Normal mode, and 4.872 V and 2.48 V for High mode, with the ripple variation of 20–60 mV. The proposed converter has been designed in a standard 0.35 μm CMOS technology and with conversion efficiencies up to 97–98% is in agreement with state-of-the-art SC converter designs. It produces the maximum load currents of 0.21 mA and 0.37 mA for Normal and High modes respectively. Due to the flexible gain accessibility and fast response time with only two clock cycles required for steady state outputs, this converter can be applicable for multi-function wearable devices, comprised of various integrated electronic modules

Low voltage dc to dc converter-regulator with minimum external magnetic field disturbance final report, 1 jun. 1954 - 30 jun. 1965

Engineering developments for low voltage dc to dc converter-regulator with minimum external magnetic field disturbanc

Capacitorless DC–DC regulator as a candidate topology for photovoltaic solar facilities

Postprint (published version

Efficient LDO-Assisted DC/DC buck converter for integrated power management system

DC-DC Switching Converters; Voltage Linear Regulators; Linear-Assisted DC-DC Voltage Regulators.Postprint (published version

Switching-Cell Arrays - An Alternative Design Approach in Power Conversion

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting /republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other worksThe conventional design of voltage-source power converters is based on a two-level half-bridge configuration and the selection of power devices designed to meet the full application specifications (voltage, current, etc.). This leads to the need to design and optimize a large number of different devices and their ancillary circuitry and prevents taking advantage from scale economies. This paper proposes a paradigm shift in the design of power converters through the use of a novel configurable device consisting on a matrix arrangement of highly-optimized switching cells at a single voltage class. Each switching cell consists of a controlled switch with antiparallel diode together with a self-powered gate driver. By properly interconnecting the switching cells, the switching cell array (SCA) can be configured as a multilevel active-clamped leg with different number of levels. Thus, the SCA presents adjustable voltage and current ratings, according to the selected configuration. For maximum compactness, the SCA can be conceived to be only configurable by the device manufacturer upon the customer needs. For minimum cost, it can also be conceived to be configurable by the customer, leading to field-configurable SCAs. Experimental results of a 6x3 field-configurable SCA are provided to illustrate and validate this design approach.Peer ReviewedPostprint (author's final draft

Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm

A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 μm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 [email protected] V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

Dual frequency receiver system for Mariner 1967 to Venus Final engineering report

Dual frequency receiver system for inclusion in Mariner 1967 spacecraft payload for use in measuring Venusian ionosphere and atmosphere by radio occultatio