624 research outputs found
Synthesis and Optimization of Reversible Circuits - A Survey
Reversible logic circuits have been historically motivated by theoretical
research in low-power electronics as well as practical improvement of
bit-manipulation transforms in cryptography and computer graphics. Recently,
reversible circuits have attracted interest as components of quantum
algorithms, as well as in photonic and nano-computing technologies where some
switching devices offer no signal gain. Research in generating reversible logic
distinguishes between circuit synthesis, post-synthesis optimization, and
technology mapping. In this survey, we review algorithmic paradigms ---
search-based, cycle-based, transformation-based, and BDD-based --- as well as
specific algorithms for reversible synthesis, both exact and heuristic. We
conclude the survey by outlining key open challenges in synthesis of reversible
and quantum logic, as well as most common misconceptions.Comment: 34 pages, 15 figures, 2 table
Architectures for soft-decision decoding of non-binary codes
En esta tesis se estudia el dise¿no de decodificadores no-binarios para la correcci'on
de errores en sistemas de comunicaci'on modernos de alta velocidad. El objetivo
es proponer soluciones de baja complejidad para los algoritmos de decodificaci'on
basados en los c'odigos de comprobaci'on de paridad de baja densidad no-binarios
(NB-LDPC) y en los c'odigos Reed-Solomon, con la finalidad de implementar arquitecturas
hardware eficientes.
En la primera parte de la tesis se analizan los cuellos de botella existentes en los
algoritmos y en las arquitecturas de decodificadores NB-LDPC y se proponen soluciones
de baja complejidad y de alta velocidad basadas en el volteo de s'¿mbolos.
En primer lugar, se estudian las soluciones basadas en actualizaci'on por inundaci
'on con el objetivo de obtener la mayor velocidad posible sin tener en cuenta la
ganancia de codificaci'on. Se proponen dos decodificadores diferentes basados en
clipping y t'ecnicas de bloqueo, sin embargo, la frecuencia m'axima est'a limitada
debido a un exceso de cableado. Por este motivo, se exploran algunos m'etodos
para reducir los problemas de rutado en c'odigos NB-LDPC. Como soluci'on se
propone una arquitectura basada en difusi'on parcial para algoritmos de volteo
de s'¿mbolos que mitiga la congesti'on por rutado. Como las soluciones de actualizaci
'on por inundaci'on de mayor velocidad son sub-'optimas desde el punto de
vista de capacidad de correci'on, decidimos dise¿nar soluciones para la actualizaci'on
serie, con el objetivo de alcanzar una mayor velocidad manteniendo la ganancia
de codificaci'on de los algoritmos originales de volteo de s'¿mbolo. Se presentan dos
algoritmos y arquitecturas de actualizaci'on serie, reduciendo el 'area y aumentando
de la velocidad m'axima alcanzable. Por 'ultimo, se generalizan los algoritmos de
volteo de s'¿mbolo y se muestra como algunos casos particulares puede lograr una
ganancia de codificaci'on cercana a los algoritmos Min-sum y Min-max con una
menor complejidad. Tambi'en se propone una arquitectura eficiente, que muestra
que el 'area se reduce a la mitad en comparaci'on con una soluci'on de mapeo directo.
En la segunda parte de la tesis, se comparan algoritmos de decodificaci'on Reed-
Solomon basados en decisi'on blanda, concluyendo que el algoritmo de baja complejidad
Chase (LCC) es la soluci'on m'as eficiente si la alta velocidad es el objetivo principal. Sin embargo, los esquemas LCC se basan en la interpolaci'on, que introduce
algunas limitaciones hardware debido a su complejidad. Con el fin de reducir
la complejidad sin modificar la capacidad de correcci'on, se propone un esquema
de decisi'on blanda para LCC basado en algoritmos de decisi'on dura. Por 'ultimo
se dise¿na una arquitectura eficiente para este nuevo esquemaGarcía Herrero, FM. (2013). Architectures for soft-decision decoding of non-binary codes [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/33753TESISPremiad
NASA Space Engineering Research Center for VLSI systems design
This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design
Techniques for ubiquitous reliable data storage
This portfolio thesis documents the work undertaken by the author under the auspices of the Engineering Doctorate (EngD) programme. The research work undertaken was completed at the sponsoring company, A2E Limited.
There is a wide range of products and solutions to meet both commercial and personal electronic storage needs. This work documents research and development over a four year period into algorithms, implementations and product development for novel storage solutions for commercial and personal use. The design work and technical and business objectives were guided by the sponsoring company, A4E limited. This portfolio thesis considers the storage market at the start of the project, the commercial and technical aspects relevant to this market place and describes the development and testing of a RAID 6 algorithm in both hardware and software.
The key contributions presented in this portfolio thesis include the implementation of the smallest and fastest FPGA based Reed-Solomon RAID 6 hardware accelerator. We also present the first commercial implementation of a Reed-Solomon RAID 6 intellectual property (IP) block.
Both the hardware and software implementation are discussed in detail along with the supporting IP blocks and device drivers. Documentation of the product development stages and additional project work carried out to provide an understanding of product development stages and the requirements placed during such work are also examined. the results of testing and implementation are considered and the performance of the proposed solution is considered along with the commercial viability and success of the project
NASA Space Engineering Research Center for VLSI System Design
This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems
NASA SERC 1990 Symposium on VLSI Design
This document contains papers presented at the first annual NASA Symposium on VLSI Design. NASA's involvement in this event demonstrates a need for research and development in high performance computing. High performance computing addresses problems faced by the scientific and industrial communities. High performance computing is needed in: (1) real-time manipulation of large data sets; (2) advanced systems control of spacecraft; (3) digital data transmission, error correction, and image compression; and (4) expert system control of spacecraft. Clearly, a valuable technology in meeting these needs is Very Large Scale Integration (VLSI). This conference addresses the following issues in VLSI design: (1) system architectures; (2) electronics; (3) algorithms; and (4) CAD tools
FPGA-based architectures for next generation communications networks
This engineering doctorate concerns the application of Field Programmable Gate Array (FPGA) technology to some of the challenges faced in the design of next generation communications networks. The growth and convergence of such networks has fuelled demand for higher bandwidth systems, and a requirement to support a diverse range of payloads across the network span.
The research which follows focuses on the development of FPGA-based architectures for two important paradigms in contemporary networking - Forward Error Correction and Packet Classification. The work seeks to combine analysis of the underlying algorithms and mathematical techniques which drive these applications, with an informed approach to the design of efficient FPGA-based circuits
The Fifth NASA Symposium on VLSI Design
The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design
The 1992 4th NASA SERC Symposium on VLSI Design
Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design
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