Memristores

Mestrado em Engenharia Eletrónica e TelecomunicaçõesThe memristor was proposed by Leon Chua in 1971 only for the sake of mathematical complement, an idea that was not widely accepted by the scientific community. Only decades later, after HP’s announcement in 2008 is that the memristors started to be seen as realizable elements and not as mere mathematical curiosities. These devices feature distinct characteristics from the other known electronic devices. Besides being passive, they are characterized by the following postulates: the existence of a characteristic voltage-current loop with hysteresis and single valued in the origin, gradual decrease of the area defined by the loop with the increasing of the frequency and simply resistive behaviour for infinite frequency. As a memristive device’s response depends greatly on the amplitude and frequency characteristics of the input signal and its own internal characteristics. Therefore there is a clear need to find procedures and attributes that allow to classify and categorize various memristive devices. These attributes, in their essence, similar to the figures of merit of devices like diodes and transistors, will allow in the near future to better choose memristive devices for specific applications. To try to obtain these attributes, a morphologic analysis of the voltage-current loops’ area and length of several theoretical memristive devices models was made in MATLAB changing its internal characteristics, for arrays of frequency and amplitude values of the input signal. Afterwards, a memristor device emulator was built to corroborate the theoretical results obtained. To this end the voltage-current loops for several input values were measured and the calculation of the loops’ areas and lengths was effectuated.O memristor foi proposto por Leon Chua em 1971 apenas por uma questão de complemento matemático, uma ideia que não teve grande aceitação na comunidade científica. Só décadas mais tarde, depois do anúncio da HP em 2008 é que os memristors começaram a ser vistos como elementos realizáveis e não como meras curiosidades matemáticas. Estes dispositivos apresentam características distintas dos demais dispositivos eletrónicos conhecidos. Além de serem elementos passivos, são caracterizados pelos seguintes postulados: existência de uma curva característica tensão-corrente com histerese e valor único na origem, diminuição gradual da área definida por esta curva com o aumento da frequência e comportamento puramente resistivo do memristor quando a frequência tende para infinito. A resposta dos dispositivos memristivos depende bastante das características de amplitude e frequência do sinal de entrada e das suas próprias características internas. Por isso, há uma clara necessidade de descobrir procedimentos e atributos que permitam classificar e categorizar diferentes dispositivos memristivos. Estes atributos, na sua essência, semelhantes às figuras de mérito de dispositivos como díodos ou transístores, permitirão num futuro próximo selecionar dispositivos memristivos para aplicações específicas. Para tentar obter estes atributos, realizou-se uma análise morfológica da área e comprimento das curvas tensão-corrente de vários modelos teóricos de dispositivos memristivos em MATLAB variando as suas características internas, para conjuntos de valores de frequência e amplitude do sinal de entrada. De seguida construiu-se um emulador de um dispositivo memristivo para corroborar os resultados teóricos obtidos. Para tal mediram-se as curvas de tensão-corrente para vários valores de entrada e efetuou-se o cálculo das áreas e comprimentos dessas curvas

Memristive System Based Image Processing Technology: A Review and Perspective

Copyright: © 2021 by the authors. As the acquisition, transmission, storage and conversion of images become more efficient, image data are increasing explosively. At the same time, the limitations of conventional computational processing systems based on the Von Neumann architecture continue to emerge, and thus, improving the efficiency of image processing has become a key issue that has bothered scholars working on images for a long time. Memristors with non-volatile, synapse-like, as well as integrated storage-and-computation properties can be used to build intelligent processing systems that are closer to the structure and function of biological brains. They are also of great significance when constructing new intelligent image processing systems with non-Von Neumann architecture and for achieving the integrated storage and computation of image data. Based on this, this paper analyses the mathematical models of memristors and discusses their applications in conventional image processing based on memristive systems as well as image processing based on memristive neural networks, to investigate the potential of memristive systems in image processing. In addition, recent advances and implications of memristive system-based image processing are presented comprehensively, and its development opportunities and challenges in different major areas are explored as well. By establishing a complete spectrum of image processing technologies based on memristive systems, this review attempts to provide a reference for future studies in the field, and it is hoped that scholars can promote its development through interdisciplinary academic exchanges and cooperationNational Natural Science Foundation of China (Grant U1909201, Grant 62001149); Natural Science Foundation of Zhejiang Province (Grant LQ21F010009)

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

Nanoscale Memristor: Great potential for memory and synapse emulator for computing applications

This work reports the fabrication and electrical characterization of Metal-Insulator-Metal (MIM) devices for neuromorphic applications using zinc-tin-oxide (ZTO) and indium-gallium-zinc-oxide (IGZO) as the switching layers and molybdenum (Mo) for the devices ‘contacts. A lithographic mask was used along with physical vapor deposition (PVD) processes for the production of the different samples’ layers. Using ZTO as a switching layer in order to replace other elements that are becoming scarce such as indium or gallium is of relevant importance, therefore it was first attempted a ZTO based MIM device. Upon electrical characterization the ZTO devices show an analog behavior without the need of current compliance (being therefore self-limited), good multilevel storage property, reliability and a stable state retention for long periods of time. It is suspected a 2D type of switching mechanism, based on the tunneling through a Schottky barrier at the interface, however the details of the exact mechanism aren’t yet clear. Furthermore, the device is highly prone to interact with humidity present in the atmosphere and some fabrication steps, which is a possible explanation for the anticlockwise RESET. A second batch of ZTO devices was fabricated in order to remediate the RESET process, using a passivation step, however the RESET direction wasn’t affected although the rectification properties of the devices were enhanced. Since upon pulse testing the ZTO devices behaved erratically, this switching layer was discarded and IGZO used instead. With this alternative amorphous oxide semiconductor material, the symmetry and linearity of the conductance change was evaluated and transition from STP (Short-Term Potentiation) to LTP (Long-Term Potentiation) successfully demonstrated upon pulse repetition, showing similar decay fashion to human memory, following a Kohlrausch-Williams-Watts function (commonly called “stretched-exponential function”)

Applications of memristors in conventional analogue electronics

This dissertation presents the steps employed to activate and utilise analogue memristive devices in conventional analogue circuits and beyond. TiO2 memristors are mainly utilised in this study, and their large variability in operation in between similar devices is identified. A specialised memristor characterisation instrument is designed and built to mitigate this issue and to allow access to large numbers of devices at a time. Its performance is quantified against linear resistors, crossbars of linear resistors, stand-alone memristive elements and crossbars of memristors. This platform allows for a wide range of different pulsing algorithms to be applied on individual devices, or on crossbars of memristive elements, and is used throughout this dissertation. Different ways of achieving analogue resistive switching from any device state are presented. Results of these are used to devise a state-of-art biasing parameter finder which automatically extracts pulsing parameters that induce repeatable analogue resistive switching. IV measurements taken during analogue resistive switching are then utilised to model the internal atomic structure of two devices, via fittings by the Simmons tunnelling barrier model. These reveal that voltage pulses modulate a nano-tunnelling gap along a conical shape. Further retention measurements are performed which reveal that under certain conditions, TiO2 memristors become volatile at short time scales. This volatile behaviour is then implemented into a novel SPICE volatile memristor model. These characterisation methods of solid-state devices allowed for inclusion of TiO2 memristors in practical electronic circuits. Firstly, in the context of large analogue resistive crossbars, a crosspoint reading method is analysed and improved via a 3-step technique. Its scaling performance is then quantified via SPICE simulations. Next, the observed volatile dynamics of memristors are exploited in two separate sequence detectors, with applications in neuromorphic engineering. Finally, the memristor as a programmable resistive weight is exploited to synthesise a memristive programmable gain amplifier and a practical memristive automatic gain control circuit.Open Acces

On the Application of PSpice for Localised Cloud Security

The work reported in this thesis commenced with a review of methods for creating random binary sequences for encoding data locally by the client before storing in the Cloud. The first method reviewed investigated evolutionary computing software which generated noise-producing functions from natural noise, a highly-speculative novel idea since noise is stochastic. Nevertheless, a function was created which generated noise to seed chaos oscillators which produced random binary sequences and this research led to a circuit-based one-time pad key chaos encoder for encrypting data. Circuit-based delay chaos oscillators, initialised with sampled electronic noise, were simulated in a linear circuit simulator called PSpice. Many simulation problems were encountered because of the nonlinear nature of chaos but were solved by creating new simulation parts, tools and simulation paradigms. Simulation data from a range of chaos sources was exported and analysed using Lyapunov analysis and identified two sources which produced one-time pad sequences with maximum entropy. This led to an encoding system which generated unlimited, infinitely-long period, unique random one-time pad encryption keys for plaintext data length matching. The keys were studied for maximum entropy and passed a suite of stringent internationally-accepted statistical tests for randomness. A prototype containing two delay chaos sources initialised by electronic noise was produced on a double-sided printed circuit board and produced more than 200 Mbits of OTPs. According to Vladimir Kotelnikov in 1941 and Claude Shannon in 1945, one-time pad sequences are theoretically-perfect and unbreakable, provided specific rules are adhered to. Two other techniques for generating random binary sequences were researched; a new circuit element, memristance was incorporated in a Chua chaos oscillator, and a fractional-order Lorenz chaos system with order less than three. Quantum computing will present many problems to cryptographic system security when existing systems are upgraded in the near future. The only existing encoding system that will resist cryptanalysis by this system is the unconditionally-secure one-time pad encryption

Resistive switching in ALD metal-oxides with engineered interfaces

L'abstract è presente nell'allegato / the abstract is in the attachmen

Memcapacitors

Mestrado em Engenharia Eletrónica e TelecomunicaçõesThe present work aims to continue the study of memory devices, initiated with the prediction of the existence of memristors by Leon Chua in 1971, with the study and characterization of memcapacitors as a semiconductor two-terminal device, characterized by the non-linear relation between charge and voltage, which also present the ability to remember the voltage or charge that passes through the device, graphically represented by a graphic with hysteresis characteristics, also presenting a variable capacitance in function of the charge applied in its terminals. Here, a characterizationof the response functions to a sinusoidal periodic input with variable frequency to three mathematical models of memcapacitive systems is performed: given a memcapacitor in series with an ac input voltage source, the respective hysteresis charge-voltage plots are studied by simulations in the MATLAB environment. Next, a classification of the hysteresis plots in function of its geometry is performed, given that the crossing of such graph in the (0.0) point defines it as a type I or type II hysteresis loop. The analysis continues with the morphological identification of the area of the hysteresis curve of the first model, by varying amplitude and frequency of the input source, in such a way to compare the other models with the ideal one, as well as to take the critical frequencis from which the memcapacitance becomes constant, and thus the system becomes linear, by making the hysteresis curve to become a straight line. The area of the first model was taken by calculations with the Green theorem.O presente trabalho propõe-se a continuar o estudo dos dispositivos de memória, iniciado com a predição dos memristors por Leon Chua em 1971, por meio do estudo e caracterização dos memcapacitores como dispositivos semicondutores de dois terminais, caracterizados pela relação não linear entre carga e tensão, que apresentam capacidade de recordar a tensão ou corrente que passa pelo dispositivo, graficamente representado em forma de um gráfico com características de histerese, aprensentando também capacitância variável em função da carga aplicada em seus terminais. Aqui, uma caracterização das funções de resposta a uma entrada periódica sinusoidal com frequência variável, para três modelos matemáticos de sistemas memcapacitivos, é realizada: dado um memcapacitor em série com uma tensão de entrada ac, estuda-se as respectivas funções de histerese carga-tensão por meio de simulação em MATLAB. Em seguida, é realizada uma classificação das curvas de histerese em função da sua geometria, em que a passagem do gráfico no ponto (0,0), de origem dos planos, o define como tipo I ou tipo II. A análise prossegue com a identificação morfológica da área das curvas de histerese obtidas dos primeiro modelo teóricos em causa, variando-se, para isso, amplitude e frequência de entradas, de modo a se comparar os outros dois modelos restantes com este modelo ideal, ao mesmo tempo em que se deseja obter as frequências críticas de cada modelo, ou seja, as frequências e amplitudes a partir das quais a memcapacitância torna-se constante, e o sistema em causa, linear, fazendo então a curva de histerese degenerar para uma reta. A área do primeiro modelo foi calculada através de um algoritmo que calcula a área da curva por meio do Teorema de Green

Reliability-aware circuit design to mitigate impact of device defects and variability in emerging memristor-based applications

In the last decades, semiconductor industry has fostered a fast downscale in technology, propelling the large scale integration of CMOS-based systems. The benefits in miniaturization are numerous, highlighting faster switching frequency, lower voltage supply and higher device density. However, this aggressive scaling trend it has not been without challenges, such as leakage currents, yield reduction or the increase in the overall system power dissipation. New materials, changes in the device structures and new architectures are key to keep the miniaturization trend. It is foreseen that 2D integration will eventually come to an insurmountable physical and economic limit, in which new strategic directions are required, such as the development of new device structures, 3D architectures or heterogeneous systems that takes advantage of the best of different technologies, both the ones already consolidated as well as emergent ones that provide performance and efficiency improvements in applications. In this context, memristor arises as one of several candidates in the race to find suitable emergent devices. Memristor, a blend of the words memory and resistor, is a passive device postulated by Leon Chua in 1971. In contrast with the other fundamental passive elements, memristors have the distinctive feature of modifying their resistance according to the charge that passes through these devices, and remaining unaltered when charge no longer flows. Although when it appeared no physical device implementation was acknowledged, HP Labs claimed in 2008 the manufacture of the first real memristor. This milestone triggered an unexpectedly high research activity about memristors, both in searching new materials and structures as well as in potential applications. Nowadays, memristors are not only appreciated in memory systems by their nonvolatile storage properties, but in many other fields, such as digital computing, signal processing circuits, or non-conventional applications like neuromorphic computing or chaotic circuits. In spite of their promising features, memristors show a primarily downside: they show significant device variation and limited lifetime due degradation compared with other alternatives. This Thesis explores the challenges that memristor variation and malfunction imposes in potential applications. The main goal is to propose circuits and strategies that either avoid reliability problems or take advantage of them. Throughout a collection of scenarios in which reliability issues are present, their impact is studied by means of simulations. This thesis is contextualized and their objectives are exposed in Chapter 1. In Chapter 2 the memristor is introduced, at both conceptual and experimental levels, and different compact levels are presented to be later used in simulations. Chapter 3 deepens in the phenomena that causes the lack of reliability in memristors, and models that include these defects in simulations are provided. The rest of the Thesis covers different applications. Therefore, Chapter 4 exhibits nonvolatile memory systems, and specifically an online test method for faulty cells. Digital computing is presented in Chapter 5, where a solution for the yield reduction in logic operations due to memristors variability is proposed. Lastly, Chapter 6 reviews applications in the analog domain, and it focuses in the exploitation of results observed in faulty memristor-based interconnect mediums for chaotic systems synchronization purposes. Finally, the Thesis concludes in Chapter 7 along with perspectives about future work.Este trabajo desarrolla un novedoso dispositivo condensador basado en el uso de la nanotecnología. El dispositivo parte del concepto existente de metal-aislador-metal (MIM), pero en lugar de una capa aislante continua, se utilizan nanopartículas dieléctricas. Las nanopartículas son principalmente de óxido de silicio (sílice) y poliestireno (PS) y los valores de diámetro son 255nm y 295nm respectivamente. Las nanopartículas contribuyen a una alta relación superficie/volumen y están fácilmente disponibles a bajo costo. La tecnología de depósito desarrollada en este trabajo se basa en la técnica de electrospray, que es una tecnología de fabricación ascendente (bottom-up) que permite el procesamiento por lotes y logra un buen compromiso entre una gran superficie y un bajo tiempo de depósito. Con el objetivo de aumentar la superficie de depósito, la configuración de electrospray ha sido ajustada para permitir áreas de depósito de 1cm2 a 25cm2. El dispositivo fabricado, los llamados condensadores de metal aislante de nanopartículas (NP-MIM) ofrecen valores de capacidad más altos que un condensador convencional similar con una capa aislante continua. En el caso de los NP-MIM de sílice, se alcanza un factor de hasta 1000 de mejora de la capacidad, mientras que los NP-MIM de poliestireno exhibe una ganancia de capacidad en el rango de 11. Además, los NP-MIM de sílice muestran comportamientos capacitivos en específicos rangos de frecuencias que depende de la humedad y el grosor de la capa de nanopartículas, mientras que los NP-MIM de poliestireno siempre mantienen su comportamiento capacitivo. Los dispositivos fabricados se han caracterizado mediante medidas de microscopía electrónica de barrido (SEM) complementadas con perforaciones de haz de iones focalizados (FIB) para caracterizar la topografía de los NP-MIMs. Los dispositivos también se han caracterizado por medidas de espectroscopia de impedancia, a diferentes temperaturas y humedades. El origen de la capacitancia aumentada está asociado en parte a la humedad en las interfaces de las nanopartículas. Se ha desarrollado un modelo de un circuito basado en elementos distribuidos para ajustar y predecir el comportamiento eléctrico de los NP-MIMs. En resumen, esta tesis muestra el diseño, fabricación, caracterización y modelización de un nuevo y prometedor condensador nanopartículas metal-aislante-metal que puede abrir el camino al desarrollo de una nueva tecnología de supercondensadores MIM