Matrix Transform Imager Architecture for On-Chip Low-Power Image Processing

Camera-on-a-chip systems have tried to include carefully chosen signal processing units for better functionality, performance and also to broaden the applications they can be used for. Image processing sensors have been possible due advances in CMOS active pixel sensors (APS) and neuromorphic focal plane imagers. Some of the advantages of these systems are compact size, high speed and parallelism, low power dissipation, and dense system integration. One can envision using these chips for portable and inexpensive video cameras on hand-held devices like personal digital assistants (PDA) or cell-phones In neuromorphic modeling of the retina it would be very nice to have processing capabilities at the focal plane while retaining the density of typical APS imager designs. Unfortunately, these two goals have been mostly incompatible. We introduce our MAtrix Transform Imager Architecture (MATIA) that uses analog floating--gate devices to make it possible to have computational imagers with high pixel densities. The core imager performs computations at the pixel plane, but still has a fill-factor of 46 percent - comparable to the high fill-factors of APS imagers. The processing is performed continuously on the image via programmable matrix operations that can operate on the entire image or blocks within the image. The resulting data-flow architecture can directly perform all kinds of block matrix image transforms. Since the imager operates in the subthreshold region and thus has low power consumption, this architecture can be used as a low-power front end for any system that utilizes these computations. Various compression algorithms (e.g. JPEG), that use block matrix transforms, can be implemented using this architecture. Since MATIA can be used for gradient computations, cheap image tracking devices can be implemented using this architecture. Other applications of this architecture can range from stand-alone universal transform imager systems to systems that can compute stereoscopic depth.Ph.D.Committee Chair: Hasler, Paul; Committee Member: David Anderson; Committee Member: DeWeerth, Steve; Committee Member: Jackson, Joel; Committee Member: Smith, Mar

Congestion control for real-time interactive multimedia streams

The Internet is getting richer, and so the services. The richer the services, the more the users demand. The more they demand, the more we guarantee(1). This thesis investigates the congestion control mechanisms for interactive multimedia streaming applications. We start by raising a question as to why the congestion control schemes are not widely deployed in real-world applications, and study what options are available at present. We then discuss and show some of the good reasonings that might have made the control mechanism, specifically speaking the rate-based congestion control mechanism, not so attractive. In an effort to address the problems, we identify the existing problems from which the rate-based congestion control protocol cannot easily escape. We therefore propose a simple but novel windowbased congestion control protocol that can retain smooth throughput property while being fair when competing with TCP, yet still being responsive to the network changes. Through the extensive ns-2 simulations and the real-world experiments, we evaluate TFWC, our proposed mechanisms, and TFRC, the proposed IETF standard, in terms of network-oriented metrics (fairness, smoothness, stability, and responsive), and end-user oriented metrics (PSNR and MOS) to throughly study the protocol’s behaviors. We then discuss and conclude the options of the evaluated protocols for the real application. (1)We as congestion control mechanisms in the Internet