Analysis And Design Optimization Of Multiphase Converter

Future microprocessors pose many challenges to the power conversion techniques. Multiphase synchronous buck converters have been widely used in high current low voltage microprocessor application. Design optimization needs to be carefully carried out with pushing the envelope specification and ever increasing concentration towards power saving features. In this work, attention has been focused on dynamic aspects of multiphase synchronous buck design. The power related issues and optimizations have been comprehensively investigated in this paper. In the first chapter, multiphase DC-DC conversion is presented with background application. Adaptive voltage positioning and various nonlinear control schemes are evaluated. Design optimization are presented to achieve best static efficiency over the entire load range. Power loss analysis from various operation modes and driver IC definition are studied thoroughly to better understand the loss terms and minimize the power loss. Load adaptive control is then proposed together with parametric optimization to achieve optimum efficiency figure. New nonlinear control schemes are proposed to improve the transient response, i.e. load engage and load release responses, of the multiphase VR in low frequency repetitive transient. Drop phase optimization and PWM transition from long tri-state phase are presented to improve the smoothness and robustness of the VR in mode transition. During high frequency repetitive transient, the control loop should be optimized and nonlinear loop should be turned off. Dynamic current sharing are thoroughly studied in chapter 4. The output impedance of the multiphase v synchronous buck are derived to assist the analysis. Beat frequency is studied and mitigated by proposing load frequency detection scheme by turning OFF the nonlinear loop and introducing current protection in the control loop. Dynamic voltage scaling (DVS) is now used in modern Multi-Core processor (MCP) and multiprocessor System-on-Chip (MPSoC) to reduce operational voltage under light load condition. With the aggressive motivation to boost dynamic power efficiency, the design specification of voltage transition (dv/dt) for the DVS is pushing the physical limitation of the multiphase converter design and the component stress as well. In this paper, the operation modes and modes transition during dynamic voltage transition are illustrated. Critical dead-times of driver IC design and system dynamics are first studied and then optimized. The excessive stress on the control MOSFET which increases the reliability concern is captured in boost mode operation. Feasible solutions are also proposed and verified by both simulation and experiment results. CdV/dt compensation for removing the AVP effect and novel nonlinear control scheme for smooth transition are proposed for dealing with fast voltage positioning. Optimum phase number control during dynamic voltage transition is also proposed and triggered by voltage identification (VID) delta to further reduce the dynamic loss. The proposed schemes are experimentally verified in a 200 W six phase synchronous buck converter. Finally, the work is concluded. The references are listed

ASDTIC control and standardized interface circuits applied to buck, parallel and buck-boost dc to dc power converters

Versatile standardized pulse modulation nondissipatively regulated control signal processing circuits were applied to three most commonly used dc to dc power converter configurations: (1) the series switching buck-regulator, (2) the pulse modulated parallel inverter, and (3) the buck-boost converter. The unique control concept and the commonality of control functions for all switching regulators have resulted in improved static and dynamic performance and control circuit standardization. New power-circuit technology was also applied to enhance reliability and to achieve optimum weight and efficiency

Current-Steering Switching Policy for a SIDO Linear-Assisted Hysteretic DC/DC Converter

This paper proposes the use of linear-assisted switching power converters in the context of single-inductor dual-output (SIDO) applications. By combining a DC/DC ripplecontrolled switching power converter with the respective voltage linear regulators at each output, improved performance in terms of load and line regulations is obtained. To achieve that aim, a current-steering switching policy is proposed, together with a resource-aware circuit implementation. The ripple-based hysteretic control results in variable switching frequency to guarantee critical conduction mode (boundary of CCM and DCM).Postprint (published version

Voltage regulation of a series stacked system of digital loads by differential power processing

A modern high-end multi-core microprocessor has very stringent power supply requirements. It can draw hundreds of amperes of current at supply voltages as low as 0.8 V. As the supply voltages keep decreasing, the power delivery to meet the supply requirements is becoming increasingly difficult and inefficient. However, the presence of multiple cores in the microprocessor offers us a way to power it at a higher voltage by series-stacking the cores. Differential power processing has been shown to be an efficient way to series-stack server loads. In this work we study the dynamics of the element-to-element DPP topology implemented with bi-directional buck-boost converters. Some of its dynamic drawbacks are pointed out and a topological modification to counter those drawbacks is proposed. We then develop a linear control to regulate processor core voltages in a series stack of 4 cores. A hysteretic control to accommodate light load modes in the bi-directional regulating converters is also discussed. Both the linear and the hysteretic controller are implemented successfully in hardware and efficiency improvement due to light-load modes is demonstrated

Digitally assisted control techniques for high performance switching DC-DC converters

Digitally controlled switching DC-DC converters have recently emerged as an attractive alternative to conventional switching converters based on analog control techniques. This research focuses on eliminating the issues associated with the state of the art switching converters by proposing three novel control techniques: (1) a digitally controlled Buck-Boost converter uses a fully synthesized constant ON/OFF time-based fractional-N controller to regulate the output over a 3.3V-to-5.5V input voltage range and provides seamless transition from buck to buck-boost modes (2) a hysteretic buck converter that employs a highly digital hybrid voltage/current mode control to regulate output voltage and switching frequency independently (3) a 10MHz continuous time PID controller using time based signal processing which alleviates the speed limitations associated with conventional analog and digital. All the three techniques employ digitally assisted control techniques and require no external compensation thus making the controllers fully integrated and highly cost effective

Mixed-source charger-supply CMOS IC

The proposed research objective is to develop, test, and evaluate a mixer and charger-supply CMOS IC that derives and mixes energy and power from mixed sources to accurately supply a miniaturized system. Since the energy-dense source stores more energy than the power-dense source while the latter supplies more power than the former, the proposed research aims to develop an IC that automatically selects how much and from which source to draw power to maximize lifetime per unit volume. Today, the state of the art lacks the intelligence and capability to select the most appropriate source from which to extract power to supply the time-varying needs of a small system. As such, the underlying objective and benefit of this research is to reduce the size of a complete electronic system so that wireless sensors and biomedical implants, for example, as a whole, perform well, operate for extended periods, and integrate into tiny spaces.Ph.D

A PWM/PFM Dual-Mode DC-DC Buck Converter with Load-Dependent Efficiency-Controllable Scheme for Multi-Purpose IoT Applications

This paper presents a dual-mode DC-DC buck converter including a load-dependent, efficiency-controllable scheme to support multi-purpose IoT applications. For light-load applications, a selectable adaptive on-time pulse frequency modulation (PFM) control is proposed to achieve optimum power efficiency by selecting the optimum switching frequency according to the load current, thereby reducing unnecessary switching losses. When the inductor peak current value or converter output voltage ripple are considered in some applications, its on-time can be adjusted further. In heavy-load applications, a conventional pulse width modulation (PWM) control scheme is adopted, and its gate driver is structured to reduce dynamic current, preventing the current from shooting through the power switch. A proposed dual-mode buck converter prototype is fabricated in a 180 nm CMOS process, achieving its measured maximum efficiency of 95.7% and power density of 0.83 W/mm(2)