Investigation into yield and reliability enhancement of TSV-based three-dimensional integration circuits

Three dimensional integrated circuits (3D ICs) have been acknowledged as a promising technology to overcome the interconnect delay bottleneck brought by continuous CMOS scaling. Recent research shows that through-silicon-vias (TSVs), which act as vertical links between layers, pose yield and reliability challenges for 3D design. This thesis presents three original contributions.The first contribution presents a grouping-based technique to improve the yield of 3D ICs under manufacturing TSV defects, where regular and redundant TSVs are partitioned into groups. In each group, signals can select good TSVs using rerouting multiplexers avoiding defective TSVs. Grouping ratio (regular to redundant TSVs in one group) has an impact on yield and hardware overhead. Mathematical probabilistic models are presented for yield analysis under the influence of independent and clustering defect distributions. Simulation results using MATLAB show that for a given number of TSVs and TSV failure rate, careful selection of grouping ratio results in achieving 100% yield at minimal hardware cost (number of multiplexers and redundant TSVs) in comparison to a design that does not exploit TSV grouping ratios. The second contribution presents an efficient online fault tolerance technique based on redundant TSVs, to detect TSV manufacturing defects and address thermal-induced reliability issue. The proposed technique accounts for both fault detection and recovery in the presence of three TSV defects: voids, delamination between TSV and landing pad, and TSV short-to-substrate. Simulations using HSPICE and ModelSim are carried out to validate fault detection and recovery. Results show that regular and redundant TSVs can be divided into groups to minimise area overhead without affecting the fault tolerance capability of the technique. Synthesis results using 130-nm design library show that 100% repair capability can be achieved with low area overhead (4% for the best case). The last contribution proposes a technique with joint consideration of temperature mitigation and fault tolerance without introducing additional redundant TSVs. This is achieved by reusing spare TSVs that are frequently deployed for improving yield and reliability in 3D ICs. The proposed technique consists of two steps: TSV determination step, which is for achieving optimal partition between regular and spare TSVs into groups; The second step is TSV placement, where temperature mitigation is targeted while optimizing total wirelength and routing difference. Simulation results show that using the proposed technique, 100% repair capability is achieved across all (five) benchmarks with an average temperature reduction of 75.2? (34.1%) (best case is 99.8? (58.5%)), while increasing wirelength by a small amount

Design and fabrication of a circular Digital Variable Optical Attenuator

The second generation circular digital variable optical attenuator (CDVOA) with an effective area of 1500 μm diameter has been designed and fabricated based on SOI technology. C-band incoming Gaussian light can be reflected to an outgoing fiber from a shiny circular area, which is divided into sectors that can be individually tilted and addressed electrostatically to achieve variable light attenuation. Using a delay mask process, each movable component i) has an underlying ridge frame to maintain flatness, ii) is suspended by two micro beams at a bridge structure that connects to a handle where aluminum electrode is located underneath, and iii) is separated by wall structures at the handle area to reduce crosstalk from adjacent electrodes. Critical fabrication processes including the mirror and chip release are performed using a HF vapor phase etcher. Fluidic pressure and chip-dicing shocks are avoided. Initial results show that a mirror sector suspended by two 345 μm long beams with a cross-section of about 5×5 μm2 can be tilted to 2.8° at about 18 V driving voltage. Initial interferometric measurement gives estimated individual mirror flatness after metallic reflective coating to be about λ/15. The assembled chips are ready for further testing and characterization

Optical network-on-chip architectures and designs

As indicated in the latest version of ITRS roadmap, optical wiring is a viable interconnection technology for future SoC/SiC/SiP designs that can provide broad band data transfer rates unmatchable by the existing metal/low-k dielectric interconnects. In this dissertation study, a set of different optical interconnection architectures are presented for future on-chip optical micro-networks. Three Optical Network-on-Chip (ONoC) architectures, i.e., Wavelength Routing Optical Network-on-Chip (WRON), Redundant Wavelength Routed Optical Network (RDWRON) and Recursive Wavelength Routed Optical Network (RCWRON) are proposed. They are fully connected networks designed based on passive switching Microring Resonator (MRR) optical switches. Given enough different routing optical wavelengths, between any two nodes in the system a bi-directional communication channel can be built. WRON, RDWRON and RCWRON share the similar network structure with different specialties that fit to different applications. A new topology of packet switching NoC architecture, i.e., Quartered Recursive Diagonal Torus (QRDT) is proposed. It is designed by overlaying diagonal torus. Due to its small diameter and rich routing recourses, QRDT leads to highly scalable NoCs. By combining WRON\u27s interconnection property and QRDT\u27s network topology, a group of 2D-Torus based Packet Switching ONoC (TON) architectures is proposed. The TON is further refined to a generalized open-topology ONoC architecture, called Generalized 2D-Torus-based Optical Network-on-Chip (GTON). The communication protocol in TON is packet switching. The advantages of GTON stem from Wavelength Division Multiplexing (WDM), Direct Optical Channel (DOC) and MRR passive switching. As result, GTON architecture is highly scalable, has an ultra-high bandwidth, consumes a low power, and supports fault-tolerant routing. The work includes other issues such as channel design, analyses of the transmission power loss and the buffer

Synchronous and Concurrent Transmissions for Consensus in Low-Power Wireless

With the emergence of the Internet of Things, autonomous vehicles and the Industry 4.0, the need for dependable yet adaptive network protocols is arising. Many of these applications build their operations on distributed consensus. For example, UAVs agree on maneuvers to execute, and industrial systems agree on set-points for actuators.Moreover, such scenarios imply a dynamic network topology due to mobility and interference, for example. Many applications are mission- and safety-critical, too.Failures could cost lives or precipitate economic losses.In this thesis, we design, implement and evaluate network protocols as a step towards enabling a low-power, adaptive and dependable ubiquitous networking that enables consensus in the Internet of Things. We make four main contributions:- We introduce Orchestra that addresses the challenge of bringing TSCH (Time Slotted Channel Hopping) to dynamic networks as envisioned in the Internet of Things. In Orchestra, nodes autonomously compute their local schedules and update automatically as the topology evolves without signaling overhead. Besides, it does not require a central or distributed scheduler. Instead, it relies on the existing network stack information to maintain the schedules.- We present A2 : Agreement in the Air, a system that brings distributed consensus to low-power multihop networks. A2 introduces Synchrotron, a synchronous transmissions kernel that builds a robust mesh by exploiting the capture effect, frequency hopping with parallel channels, and link-layer security. A2 builds on top of this layer and enables the two- and three-phase commit protocols, and services such as group membership, hopping sequence distribution, and re-keying.- We present Wireless Paxos, a fault-tolerant, network-wide consensus primitive for low-power wireless networks. It is a new variant of Paxos, a widely used consensus protocol, and is specifically designed to tackle the challenges of low-power wireless networks. By utilizing concurrent transmissions, it provides a dependable low-latency consensus.- We present BlueFlood, a protocol that adapts concurrent transmissions to Bluetooth. The result is fast and efficient data dissemination in multihop Bluetooth networks. Moreover, BlueFlood floods can be reliably received by off-the-shelf Bluetooth devices such as smartphones, opening new applications of concurrent transmissions and seamless integration with existing technologies

Cryogenic Control Beyond 100 Qubits

Quantum computation has been a major focus of research in the past two decades, with recent experiments demonstrating basic algorithms on small numbers of qubits. A large-scale universal quantum computer would have a profound impact on science and technology, providing a solution to several problems intractable for classical computers. To realise such a machine, today's small experiments must be scaled up, and a system must be built which provides control and measurement of many hundreds of qubits. A device of this scale is challenging: qubits are highly sensitive to their environment, and sophisticated isolation techniques are required to preserve the qubits' fragile states. Solid-state qubits require deep-cryogenic cooling to suppress thermal excitations. Yet current state-of-the-art experiments use room-temperature electronics which are electrically connected to the qubits. This thesis investigates various scalable technologies and techniques which can be used to control quantum systems. With the requirements for semiconductor spin-qubits in mind, several custom electronic systems, to provide quantum control from deep cryogenic temperatures, are designed and measured. A system architecture is proposed for quantum control, providing a scalable approach to executing quantum algorithms on a large number of qubits. Control of a gallium arsenide qubit is demonstrated using a cryogenically operated FPGA driving custom gallium arsenide switches. The cryogenic performance of a commercial FPGA is measured, as the main logic processor in a cryogenic quantum control system, and digital-to-analog converters are analysed during cryogenic operation. Recent work towards a 100-qubit cryogenic control system is shown, including the design of interconnect solutions and multiplexing circuitry. With qubit fidelity over the fault-tolerant threshold for certain error correcting codes, accompanying control platforms will play a key role in the development of a scalable quantum machine