Design of energy efficient high speed I/O interfaces

Energy efficiency has become a key performance metric for wireline high speed I/O interfaces. Consequently, design of low power I/O interfaces has garnered large interest that has mostly been focused on active power reduction techniques at peak data rate. In practice, most systems exhibit a wide range of data transfer patterns. As a result, low energy per bit operation at peak data rate does not necessarily translate to overall low energy operation. Therefore, I/O interfaces that can scale their power consumption with data rate requirement are desirable. Rapid on-off I/O interfaces have a potential to scale power with data rate requirements without severely affecting either latency or the throughput of the I/O interface. In this work, we explore circuit techniques for designing rapid on-off high speed wireline I/O interfaces and digital fractional-N PLLs. A burst-mode transmitter suitable for rapid on-off I/O interfaces is presented that achieves 6 ns turn-on time by utilizing a fast frequency settling ring oscillator in digital multiplying delay-locked loop and a rapid on-off biasing scheme for current mode output driver. Fabricated in 90 nm CMOS process, the prototype achieves 2.29 mW/Gb/s energy efficiency at peak data rate of 8 Gb/s. A 125X (8 Gb/s to 64 Mb/s) change in effective data rate results in 67X (18.29 mW to 0.27 mW) change in transmitter power consumption corresponding to only 2X (2.29 mW/Gb/s to 4.24 mW/Gb/s) degradation in energy efficiency for 32-byte long data bursts. We also present an analytical bit error rate (BER) computation technique for this transmitter under rapid on-off operation, which uses MDLL settling measurement data in conjunction with always-on transmitter measurements. This technique indicates that the BER bathtub width for 10^(−12) BER is 0.65 UI and 0.72 UI during rapid on-off operation and always-on operation, respectively. Next, a pulse response estimation-based technique is proposed enabling burst-mode operation for baud-rate sampling receivers that operate over high loss channels. Such receivers typically employ discrete time equalization to combat inter-symbol interference. Implementation details are provided for a receiver chip, fabricated in 65nm CMOS technology, that demonstrates efficacy of the proposed technique. A low complexity pulse response estimation technique is also presented for low power receivers that do not employ discrete time equalizers. We also present techniques for implementation of highly digital fractional-N PLL employing a phase interpolator based fractional divider to improve the quantization noise shaping properties of a 1-bit ∆Σ frequency-to-digital converter. Fabricated in 65nm CMOS process, the prototype calibration-free fractional-N Type-II PLL employs the proposed frequency-to-digital converter in place of a high resolution time-to-digital converter and achieves 848 fs rms integrated jitter (1 kHz-30 MHz) and -101 dBc/Hz in-band phase noise while generating 5.054 GHz output from 31.25 MHz input

All-Digital Phase-Locked Loop for Radio Frequency Synthesis

It has been a constant challenge in wireless system design to meet the growing demand for an ever higher data rate and more diversified functionality at minimal cost and power consumption. The key lies in exploiting the phenomenal success of CMOS technology scaling for high-level integration. This underlies the paradigm shift in the field of integrated circuit (IC) design to one that increasingly favours digital circuits as opposed to their analog counterparts. With radio transceiver design for wireless systems in particular, a noticeable trend is the introduction of digital-intensive solutions for traditional analog functions. A prominent example is the emergence of the all-digital phase-locked loop (ADPLL) architectures for frequency synthesis. By avoiding traditional analog blocks, the ADPLL brings the benefits of high-level integration and improved programmability. This thesis presents ADPLL frequency synthesizer design, highlighting practical design considerations and technical innovations. Three prototype designs using a 65-nm CMOS technology are presented. The first example address a low-power ADPLL design for 2.4-GHz ISM (Industrial, Scientific, Medical) band frequency synthesis. A high-speed topology is employed in the implementation for the variable phase accumulator to count full cycles of the radio frequency (RF) output. A simple technique based on a short delay line in the reference signal path allows the time-to-digital converter (TDC) core to operate at a low duty cycle with approximately 95% reduction in its average power consumption. The ADPLL incorporates a two-point modulation scheme with an adaptive gain calibration to allow for direct frequency modulation. The second implementation is a wide-band ADPLL-based frequency synthesizer for cognitive radio sensor units. It employs a digitally controlled ring oscillator with an LC tank introduced to extend the tuning range and reduce power dissipation. An adaptive frequency calibration technique based on binary search is used for fast frequency settling. The third implementation is another wideband ADPLL frequency synthesizer. At the architectural level, separation of coarse-tune and fine-tune branches results in a word length reduction for both of them and allows the coarse tuning logic to be powered off or clock gated during normal operation, which led to a significant reduction in the area and power consumption for the digital logic and simplified the digital design. A dynamic binary search technique was proposed to achieve further improved frequency calibration speed compared with previous techniques. In addition, an original technique was employed for the frequency tuning of the wideband ring oscillator to allow for compact design and excellent linearity

High Performance Local Oscillator Design for Next Generation Wireless Communication

Local Oscillator (LO) is an essential building block in modern wireless radios. In modern wireless radios, LO often serves as a reference of the carrier signal to modulate or demod- ulate the outgoing or incoming data. The LO signal should be a clean and stable source, such that the frequency or timing information of the carrier reference can be well-defined. However, as radio architecture evolves, the importance of LO path design has become much more important than before. Of late, many radio architecture innovations have exploited sophisticated LO generation schemes to meet the ever-increasing demands of wireless radio performances. The focus of this thesis is to address challenges in the LO path design for next-generation high performance wireless radios. These challenges include (1) Congested spectrum at low radio frequency (RF) below 5GHz (2) Continuing miniaturization of integrated wireless radio, and (3) Fiber-fast (>10Gb/s) mm-wave wireless communication. The thesis begins with a brief introduction of the aforementioned challenges followed by a discussion of the opportunities projected to overcome these challenges. To address the challenge of congested spectrum at frequency below 5GHz, novel ra- dio architectures such as cognitive radio, software-defined radio, and full-duplex radio have drawn significant research interest. Cognitive radio is a radio architecture that opportunisti- cally utilize the unused spectrum in an environment to maximize spectrum usage efficiency. Energy-efficient spectrum sensing is the key to implementing cognitive radio. To enable energy-efficient spectrum sensing, a fast-hopping frequency synthesizer is an essential build- ing block to swiftly sweep the carrier frequency of the radio across the available spectrum. Chapter 2 of this thesis further highlights the challenges and trade-offs of the current LO gen- eration scheme for possible use in sweeping LO-based spectrum analysis. It follows by intro- duction of the proposed fast-hopping LO architecture, its implementation and measurement results of the validated prototype. Chapter 3 proposes an embedded phase-shifting LO-path design for wideband RF self-interference cancellation for full-duplex radio. It demonstrates a synergistic design between the LO path and signal to perform self-interference cancellation. To address the challenge of continuing miniaturization of integrated wireless radio, ring oscillator-based frequency synthesizer is an attractive candidate due to its compactness. Chapter 4 discussed the difficulty associated with implementing a Phase-Locked Loop (PLL) with ultra-small form-factor. It further proposes the concept sub-sampling PLL with time- based loop filter to address these challenges. A 65nm CMOS prototype and its measurement result are presented for validation of the concept. In shifting from RF to mm-wave frequencies, the performance of wireless communication links is boosted by significant bandwidth and data-rate expansion. However, the demand for data-rate improvement is out-pacing the innovation of radio architectures. A >10Gb/s mm-wave wireless communication at 60GHz is required by emerging applications such as virtual-reality (VR) headsets, inter-rack data transmission at data center, and Ultra-High- Definition (UHD) TV home entertainment systems. Channel-bonding is considered to be a promising technique for achieving >10Gb/s wireless communication at 60GHz. Chapter 5 discusses the fundamental radio implementation challenges associated with channel-bonding for 60GHz wireless communication and the pros and cons of prior arts that attempted to address these challenges. It is followed by a discussion of the proposed 60GHz channel- bonding receiver, which utilizes only a single PLL and enables both contiguous and non- contiguous channel-bonding schemes. Finally, Chapter 6 presents the conclusion of this thesis

A Low Jitter Wideband Fractional-N Subsampling Phase Locked Loop (SSPLL)

Frequency synthesizers have become a crucial building block in the evolution of modern communication systems and consumer electronics. The spectral purity performance of frequency synthesizers limits the achievable data-rate and presents a noise-power tradeoff. For communication standards such as LTE where the channel spacing is a few kHz, the synthesizers must provide high frequencies with sufficiently wide frequency tuning range and fine frequency resolutions. Such stringent performance must be met with a limited power and small chip area. In this thesis a wideband fractional-N frequency synthesizer based on a subsampling phase locked loop (SSPLL) is presented. The proposed synthesizer which has a frequency resolution less than 100Hz employs a digital fractional controller (DFC) and a 10-bit digital-to-time converter (DTC) to delay the rising edges of the reference clock to achieve fractional phase lock. For fast convergence of the delay calibration, a novel two-step delay correlation loop (DCL) is employed. Furthermore, to provide optimum settling and jitter performance, the loop transfer characteristics during frequency acquisition and phase-lock are decoupled using a dual input loop filter (DILF). The fractional-N sub-sampling PLL (FNSSPLL) is implemented in a TSMC 40nm CMOS technology and occupies a total active area of 0.41mm^2. The PLL operates over frequency range of 2.8 GHz to 4.3 GHz (42% tuning range) while consuming 9.18mW from a 1.1V supply. The integrated jitter performance is better than 390 fs across all fractional frequency channel. The worst case fractional spur of -48.3 dBc occurs at a 650 kHz offset for a 3.75GHz fractional channel. The in-band phase noise measured at a 200 kHz offset is -112.5 dBc/Hz

Jitter reduction techniques for digital audio.

by Tsang Yick Man, Steven.Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.Includes bibliographical references (leaves 94-99).ABSTRACT --- p.iACKNOWLEDGMENT --- p.iiLIST OF GLOSSARY --- p.iiiChapter 1 --- INTRODUCTION --- p.1Chapter 1.1 --- What is the jitter ？ --- p.3Chapter 2 --- WHY DOES JITTER OCCUR IN DIGITAL AUDIO ？ --- p.4Chapter 2.1 --- Poorly-designed Phase Locked Loop ( PLL ) --- p.4Chapter 2.1.1 --- Digital data problem --- p.7Chapter 2.2 --- Sampling jitter or clock jitter ( Δti) --- p.9Chapter 2.3 --- Waveform distortion --- p.12Chapter 2.4 --- Logic induced jitter --- p.17Chapter 2.4.1 --- Digital noise mechanisms --- p.20Chapter 2.4.2 --- Different types of D-type flop-flip chips are linked below for ease of comparison --- p.21Chapter 2.4.3 --- Ground bounce --- p.22Chapter 2.5 --- Power supply high frequency noise --- p.23Chapter 2.6 --- Interface Jitter --- p.25Chapter 2.7 --- Cross-talk --- p.28Chapter 2.8 --- Inter-Symbol-Interference (ISI) --- p.28Chapter 2.9 --- Baseline wander --- p.29Chapter 2.10 --- Noise jitter --- p.30Chapter 2.11 --- FIFO jitter reduction chips --- p.31Chapter 3 --- JITTER REDUCTION TECHNIQUES --- p.33Chapter 3.1 --- Why using two-stage phase-locked loop (PLL ) ？Chapter 3.1.1 --- The PLL circuit components --- p.35Chapter 3.1.2 --- The PLL timing specifications --- p.36Chapter 3.2 --- Analog phase-locked loop (APLL ) circuit usedin second stage --- p.38Chapter 3.3 --- All digital phase-locked loop (ADPLL ) circuit used in second stage --- p.40Chapter 3.4 --- ADPLL design --- p.42Chapter 3.4.1 --- "Different of K counter value of ADPLL are listed for comparison with M=512, N=256, Kd=2" --- p.46Chapter 3.4.2 --- Computer simulated results and experimental results of the ADPLL --- p.47Chapter 3.4.3 --- PLL design notes --- p.58Chapter 3.5 --- Different of the all digital Phase-Locked Loop (ADPLL ) and the analogue Phase-Locked Loop (APLL ) are listed for comparison --- p.65Chapter 3.6 --- Discrete transistor oscillator --- p.68Chapter 3.7 --- Discrete transistor oscillator circuit operation --- p.69Chapter 3.8 --- The advantage and disadvantage of using external discrete oscillator --- p.71Chapter 3.9 --- Background of using high-precision oscillators --- p.72Chapter 3.9.1 --- The temperature compensated crystal circuit operation --- p.73Chapter 3.9.2 --- The temperature compensated circuit design notes --- p.75Chapter 3.10 --- The discrete voltage reference circuit operation --- p.76Chapter 3.10.1 --- Comparing the different types of Op-amps that can be used as a voltage comparator --- p.79Chapter 3.10.2 --- Precaution of separate CMOS chips Vdd and Vcc --- p.80Chapter 3.11 --- Board level jitter reduction method --- p.81Chapter 3.12 --- Digital audio interface chips --- p.82Chapter 3.12.1 --- Different brand of the digital interface receiver (DIR) chips and clock modular are listed for comparison --- p.84Chapter 4. --- APPLICATION CIRCUIT BLOCK DIAGRAMS OF JITTER REDUCTION AND CLOCK RECOVERY --- p.85Chapter 5 --- CONCLUSIONS --- p.90Chapter 5.1 --- Summary of the research --- p.90Chapter 5.2 --- Suggestions for further development --- p.92Chapter 5.3 --- Instrument listing that used in this thesis --- p.93Chapter 6 --- REFERENCES --- p.94Chapter 7 --- APPENDICES --- p.100Chapter 7.1.1 --- Phase instability in frequency dividersChapter 7.1.2 --- The effect of clock tree on Tskew on ASIC chipChapter 7.1.3 --- Digital audio transmission----Why jitter is important?Chapter 7.1.4 --- Overview of digital audio interface data structuresChapter 7.1.5 --- Typical frequency Vs temperature variations curve of Quartz crystalsChapter 7.2 --- IC specification used in these research projec

Modelling, simulation and control of photovoltaic converter systems

The thesis follows the development of an advanced solar photovoltaic power conversion system from first principles. It is divided into five parts. The first section shows the development of a circuit-based simulation model of a photovoltaic (PV) cell within the 'SABER' simulator environment. Although simulation models for photovoltaic cells are available these are usually application specific, mathematically intensive and not suited to the development of power electronics. The model derived within the thesis is a circuit-based model that makes use of a series of current/voltage data sets taken from an actual cell in order to define the relationships between the cell double-exponential model parameters and the environmental parameters of temperature and irradiance. Resulting expressions define a 'black box' model, and the power electronics designer may simply specify values of temperature and irradiance to the model, and the simulated electrical connections to the cell provide the appropriate I/V characteristic. The second section deals with the development of a simulation model of an advanced PVaware DC-DC converter system. This differs from the conventional in that by using an embedded maximum power tracking system within a conventional linear feedback control arrangement it addresses the problem of loads which may not require the level of power available at the maximum power point, but is also able to drive loads which consistently require a maximum power feed such as a grid-coupled inverter. The third section details a low-power implementation of the above system in hardware. This shows the viability of the new, fast embedded maximum power tracking system and also the advantages of the system in terms of speed and response time over conventional systems. The fourth section builds upon the simulation model developed in the second section by adding an inverter allowing AC loads (including a utility) to be driven. The complete system is simulated and a set of results obtained showing that the system is a usable one. The final section describes the construction and analysis of a complete system in hardware (c. 500W) and identifies the suitability of the system to appropriate applications

Signal Encoding and Digital Signal Processing in Continuous Time

This work investigates signal encoding in, and architectures of, digital signal processing systems that function in continuous time (CT). Unlike conventional digital signal processors (DSPs), which rely on a clock to dictate the sampling times of an analog-to-digital converter (ADC) and to provide the tap delay timing, CT DSPs function entirely in continuous time, without a sampling or a synchronizing clock. The samples of a CT DSP system are generated and processed only when some measure of the input signal crosses a predetermined threshold. The effective sampling rate and the dynamic power dissipation of a CT digital system automatically adapt to the activity of the input signal. The properties of signals sampled in continuous time are investigated in this thesis. A technique for reducing the effective sampling rate of a CT system is presented, in which the digital signal encoding is varied by adjusting the resolution according to a property of the input. A variable-resolution system leads to a decrease in the number of samples generated, a reduction in the power dissipation and a reduction in the effective chip area of a CT DSP, all without sacrificing in-band performance. The properties of several asynchronous signal-driven sampling techniques are analyzed and compared. The architecture and signal encoding of CT DSPs for signals in the lower gigahertz frequency range are investigated, with consideration of speed and accuracy limitations in the context of submicron CMOS technologies. A per-edge digital signal encoding technique is developed, which bypasses timing problems of processing high-speed digital signals; the properties of per-edge encoded signals are discussed. The design considerations of a low-resolution per-edge-encoded gigahertz-range CT DSP are discussed and an implementation for a possible application is detailed. A prototype chip has been fabricated in ST 65 nm CMOS technology, which has a compact processor core area of 0.073 mm^2. The implemented CT digital processor achieves SNDR of over 20 dB with 3 bits of resolution and a maximum usable -3 dB bandwidth of 0.8 GHz to 3.2 GHz. The processor can be configured as a one-tap to six-tap CT FIR filter and has an active power dissipation that varies from 0.27 mW to 9.5 mW, depending on the amplitude and frequency of the input signal

Proceedings of the Sixteenth Annual Precise Time and Time Interval (PTTI) Applications and Planning Meeting

The effects of ionospheric and tropospheric propagation on time and frequency transfer, advances in the generation of precise time and frequency, time transfer techniques and filtering and modeling were among the topics emphasized. Rubidium and cesium frequency standard, crystal oscillators, masers, Kalman filters, and atomic clocks were discussed

Large space structures and systems in the space station era: A bibliography with indexes (supplement 05)

Bibliographies and abstracts are listed for 1363 reports, articles, and other documents introduced into the NASA scientific and technical information system between January 1, 1991 and July 31, 1992. Topics covered include technology development and mission design according to system, interactive analysis and design, structural and thermal analysis and design, structural concepts and control systems, electronics, advanced materials, assembly concepts, propulsion and solar power satellite systems