Expanded delta networks for very large parallel computers

In this paper we analyze a generalization of the traditional delta network, introduced by Patel [21], and dubbed Expanded Delta Network (EDN). These networks provide in general multiple paths that can be exploited to reduce contention in the network resulting in increased performance. The crossbar and traditional delta networks are limiting cases of this class of networks. However, the delta network does not provide the multiple paths that the more general expanded delta networks provide, and crossbars are to costly to use for large networks. The EDNs are analyzed with respect to their routing capabilities in the MIMD and SIMD models of computation.The concepts of capacity and clustering are also addressed. In massively parallel SIMD computers, it is the trend to put a larger number processors on a chip, but due to I/O constraints only a subset of the total number of processors may have access to the network. This is introduced as a Restricted Access Expanded Delta Network of which the MasPar MP-1 router network is an example

Power-Aware Datacenter Networking and Optimization

Present-day datacenter networks (DCNs) are designed to achieve full bisection bandwidth in order to provide high network throughput and server agility. However, the average utilization of typical DCN infrastructure is below 10% for significant time intervals. As a result, energy is wasted during these periods. In this thesis we analyze traffic behavior of datacenter networks using traces as well as simulated models. Based on the insight developed, we present techniques to reduce energy waste by making energy use scale linearly with load. The solutions developed are analyzed via simulations, formal analysis, and prototyping. The impact of our work is significant because the energy savings we obtain for networking infrastructure of DCNs are near optimal. A key finding of our traffic analysis is that network switch ports within the DCN are grossly under-utilized. Therefore, the first solution we study is to modify the routing within the network to force most traffic to the smallest of switches. This increases the hop count for the traffic but enables the powering off of many switch ports. The exact extent of energy savings is derived and validated using simulations. An alternative strategy we explore in this context is to replace about half the switches with fewer switches that have higher port density. This has the effect of enabling even greater traffic consolidation, thus enabling even more ports to sleep. Finally, we explore a third approach in which we begin with end-to-end traffic models and incrementally build a DCN topology that is optimized for that model. In other words, the network topology is optimized for the potential use of the datacenter. This approach makes sense because, as other researchers have observed, the traffic in a datacenter is heavily dependent on the primary use of the datacenter. A second line of research we undertake is to merge traffic in the analog domain prior to feeding it to switches. This is accomplished by use of a passive device we call a merge network. Using a merge network enables us to attain linear scaling of energy use with load regardless of datacenter traffic models. The challenge in using such a device is that layer 2 and layer 3 protocols require a one-to-one mapping of hardware addresses to IP (Internet Protocol) addresses. We overcome this problem by building a software shim layer that hides the fact that traffic is being merged. In order to validate the idea of a merge network, we build a simple mere network for gigabit optical interfaces and demonstrate correct operation at line speeds of layer 2 and layer 3 protocols. We also conducted measurements to study how traffic gets mixed in the merge network prior to being fed to the switch. We also show that the merge network uses only a fraction of a watt of power, which makes this a very attractive solution for energy efficiency. In this research we have developed solutions that enable linear scaling of energy with load in datacenter networks. The different techniques developed have been analyzed via modeling and simulations as well as prototyping. We believe that these solutions can be easily incorporated into future DCNs with little effort

Performance evaluation of network-on-chip interconnect architectures

With a communication design style, Network-on-Chips (NoCs) have been proposed as a new Multi-Processor System-on-Chip paradigm. Simulation and functional validation are essential to assess the correctness and performance of the NoC design. In this thesis, a cycle-accurate NoC simulation system in Verilog HDL is developed to evaluate the performance of various NoC architectures. First, a library of NoC components is developed based on an existing design. Each NoC architecture to be evaluated is constructed from the library according to the topology description which specifies the network topology, network size, and routing algorithm. The network performance of four NoC architectures under uniform and three non-uniform traffic patterns is tested on ModelSim 6.4. The developed NoC simulation system provides useful resources for the future development of the FPGA-based NoC emulation system

Efficient parallel processing with optical interconnections

With the advances in VLSI technology, it is now possible to build chips which can each contain thousands of processors. The efficiency of such chips in executing parallel algorithms heavily depends on the interconnection topology of the processors. It is not possible to build a fully interconnected network of processors with constant fan-in/fan-out using electrical interconnections. Free space optics is a remedy to this limitation. Qualities exclusive to the optical medium are its ability to be directed for propagation in free space and the property that optical channels can cross in space without any interference. In this thesis, we present an electro-optical interconnected architecture named Optical Reconfigurable Mesh (ORM). It is based on an existing optical model of computation. There are two layers in the architecture. The processing layer is a reconfigurable mesh and the deflecting layer contains optical devices to deflect light beams. ORM provides three types of communication mechanisms. The first is for arbitrary planar connections among sets of locally connected processors using the reconfigurable mesh. The second is for arbitrary connections among N of the processors using the electrical buses on the processing layer and N2 fixed passive deflecting units on the deflection layer. The third is for arbitrary connections among any of the N2 processors using the N2 mechanically reconfigurable deflectors in the deflection layer. The third type of communication mechanisms is significantly slower than the other two. Therefore, it is desirable to avoid reconfiguring this type of communication during the execution of the algorithms. Instead, the optical reconfiguration can be done before the execution of each algorithm begins. Determining a right configuration that would be suitable for the entire configuration of a task execution is studied in this thesis. The basic data movements for each of the mechanisms are studied. Finally, to show the power of ORM, we use all three types of communication mechanisms in the first O(logN) time algorithm for finding the convex hulls of all figures in an N x N binary image presented in this thesis

Microring-Resonator-Based Switch Architectures for Optical Networks

Integrated silicon photonics provides a promising platform for chip-based, high-speed optical signal processing due to its compatibility with complementary metal-oxide semiconductor (CMOS) fabrication processes. They are attracting significant research and development interest globally and making a huge impact on green information and communication technologies, and high-performance computing systems. Microring resonators (MRRs) show the versatility to implement a variety of network functions, compact footprint, and complementary metal-oxide semiconductor compatibility, and demonstrate the viability applied in photonic integrated technologies for both chip level and board-to-board interconnects. Furthermore, MRRs have excellent wavelength selection properties and can be used to design tunable filters, modulators, wavelength converters, and switches that are critical components for optical interconnects. The research work of this dissertation is focused on investigating how to develop MRR-based switches and switch architectures for possible applications not only in optical interconnection networks but also in flexible-grid on-chip networks for optical communication systems. The basic properties and performances of the MRR switches and the MRR switch architectures related to their applications in the networks are examined. In particular, how to design and how to configure high performance, bandwidth variable, low insertion loss, and weak crosstalk MRR-based switches and switch architectures are investigated for applications in optical interconnection networks and in flexible-grid on-chip networks for optical communication systems. The works include several parts as follows. The physical characteristics of microring resonator switching devices are thoroughly analyzed using a model based on the field coupling matrix theory. The spectral response and insertion loss properties of these switching elements are simulated using the developed model. Then we investigate the optimal design of high-order MRR-based switch devices. Spectral shaping of the passbands of microring resonator switches is studied. Multistage high-order microring resonator-based optical switch structures are proposed to achieve steep-edge flat-top spectral passband. Using the transfer matrix analysis model, the spectral response behaviors of the switch structures are simulated. The performances of the proposed multistage high-order microring resonator-based optical switch structures and the high-order microring-resonator-based optical switch structures without stages are studied and compared. Two types of MRR-based switch architectures are proposed to realize variable output bandwidths varying from 0 to 4 THz. One consists of 320, 160, and 80 third-order MRR switches with -3 dB passband widths of 12.5, 25, and 50 GHz, respectively. Another one is two-stage switch structure. In the first stage there are 4 third-order MRR switches with the passband widths of 1 THz. In second stage, there are 80, 40, 20 third-order MRR switches with the passband widths of 12.5, 25, and 50 GHz, respectively. Their insertion losses and crosstalks in the worst cases are numerically analyzed and compared in order to show the feasibility for the architectures to be applied in flexible optical networks. MRR-based bandwidth-variable wavelength selective switch architectures with multiple input and output ports are proposed for flexible optical networks. The light transmission behaviors of a 1 by N MRR-based WSS are analyzed in detail based on numerical simulation using transfer matrix theory. Two types of N by N MRR-based WSS architectures consisting of MRR-based WSSs and MRR-based WSSs, and MRR-based WSSs and optical couplers are proposed. The performances of the proposed architectures are studied. Scalable optical interconnections based on MRRs are proposed, which consist mainly of microring resonator devices: microring lasers, microring switches, microring de-multiplexers, and integrated photo-dectors. Their throughput capacities, end-to-end time latencies, and transmission packet loss rates are evaluated using OMNet++. In summary, the research of the dissertation contributes to develop high performance, variable bandwidth, low insertion loss, and low crosstalk MRR-based optical switches and switch architectures to adapt to dynamic source allocation of flexible-grid optical networks

Measuring and Understanding Throughput of Network Topologies

High throughput is of particular interest in data center and HPC networks. Although myriad network topologies have been proposed, a broad head-to-head comparison across topologies and across traffic patterns is absent, and the right way to compare worst-case throughput performance is a subtle problem. In this paper, we develop a framework to benchmark the throughput of network topologies, using a two-pronged approach. First, we study performance on a variety of synthetic and experimentally-measured traffic matrices (TMs). Second, we show how to measure worst-case throughput by generating a near-worst-case TM for any given topology. We apply the framework to study the performance of these TMs in a wide range of network topologies, revealing insights into the performance of topologies with scaling, robustness of performance across TMs, and the effect of scattered workload placement. Our evaluation code is freely available

Multi-Band Optical Networks Capacity, Energy, and Techno-Economic Assessment

L'abstract è presente nell'allegato / the abstract is in the attachmen