575 research outputs found
A 77.3-dB SNDR 62.5-kHz Bandwidth Continuous-Time Noise-Shaping SAR ADC With Duty-Cycled G<sub>m</sub>-C Integrator
This article presents a first-order continuous-time (CT) noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC). Different from other NS-SAR ADCs in literature, which are discrete-time (DT), this ADC utilizes a CT Gm-C integrator to realize an inherent anti-aliasing function. To cope with the timing conflict between the DT SAR ADC and the CT integrator, the sampling switch of the SAR ADC is removed, and the integrator is duty cycled to leave 5% of the sampling clock period for the SAR conversion. Redundancy is added to track the varying ADC input due to the absence of the sampling switch. A theoretical analysis shows that the 5% duty-cycling has negligible effects on the signal transfer function (STF) and the noise transfer function. The output swing and linearity requirements for the integrator are also relaxed thanks to the inherent feedforward path in the NS-SAR ADC architecture. Fabricated in 65-nm CMOS, the prototype achieves 77.3-dB peak signal-to-noise and distortion ratio (SNDR) in a 62.5-kHz bandwidth while consuming 13.5μ W, leading to a Schreier figure of merit (FoM) of 174.0 dB. Moreover, it provides 15-dB attenuation in the alias band.</p
Interface Circuits for Microsensor Integrated Systems
ca. 200 words; this text will present the book in all promotional forms (e.g. flyers). Please describe the book in straightforward and consumer-friendly terms. [Recent advances in sensing technologies, especially those for Microsensor Integrated Systems, have led to several new commercial applications. Among these, low voltage and low power circuit architectures have gained growing attention, being suitable for portable long battery life devices. The aim is to improve the performances of actual interface circuits and systems, both in terms of voltage mode and current mode, in order to overcome the potential problems due to technology scaling and different technology integrations. Related problems, especially those concerning parasitics, lead to a severe interface design attention, especially concerning the analog front-end and novel and smart architecture must be explored and tested, both at simulation and prototype level. Moreover, the growing demand for autonomous systems gets even harder the interface design due to the need of energy-aware cost-effective circuit interfaces integrating, where possible, energy harvesting solutions. The objective of this Special Issue is to explore the potential solutions to overcome actual limitations in sensor interface circuits and systems, especially those for low voltage and low power Microsensor Integrated Systems. The present Special Issue aims to present and highlight the advances and the latest novel and emergent results on this topic, showing best practices, implementations and applications. The Guest Editors invite to submit original research contributions dealing with sensor interfacing related to this specific topic. Additionally, application oriented and review papers are encouraged.
Robust sigma delta converters : and their application in low-power highly-digitized flexible receivers
In wireless communication industry, the convergence of stand-alone, single application transceiver IC’s into scalable, programmable and platform based transceiver ICs, has led to the possibility to create sophisticated mobile devices within a limited volume. These multi-standard (multi-mode), MIMO, SDR and cognitive radios, ask for more adaptability and flexibility on every abstraction level of the transceiver. The adaptability and flexibility of the receive paths require a digitized receiver architecture in which most of the adaptability and flexibility is shifted in the digital domain. This trend to ask for more adaptability and flexibility, but also more performance, higher efficiency and an increasing functionality per volume, has a major impact on the IP blocks such systems are built with. At the same time the increasing requirement for more digital processing in the same volume and for the same power has led to mainstream CMOS feature size scaling, leading to smaller, faster and more efficient transistors, optimized to increase processing efficiency per volume (smaller area, lower power consumption, faster digital processing). As wireless receivers is a comparably small market compared to digital processors, the receivers also have to be designed in a digitally optimized technology, as the processor and transceiver are on the same chip to reduce device volume. This asks for a generalized approach, which maps application requirements of complex systems (such as wireless receivers) on the advantages these digitally optimized technologies bring. First, the application trends are gathered in five quality indicators being: (algorithmic) accuracy, robustness, flexibility, efficiency, and emission, of which the last one is not further analyzed in this thesis. Secondly, using the quality indicators, it is identified that by introducing (or increasing) digitization at every abstraction level of a system, the advantages of modern digitally optimized technologies can be exploited. For a system on a chip, these abstraction levels are: system/application level, analog IP architecture level, circuit topology level and layout level. In this thesis, the quality indicators together with the digitization at different abstraction levels are applied to S¿ modulators. S¿ modulator performance properties are categorized into the proposed quality indicators. Next, it is identified what determines the accuracy, robustness, flexibility and efficiency of a S¿ modulator. Important modulator performance parameters, design parameter relations, and performance-cost relations are derived. Finally, several implementations are presented, which are designed using the found relations. At least one implementation example is shown for each level of digitization. At system level, a flexible (N)ZIF receiver architecture is digitized by shifting the ADC closer to the antenna, reducing the amount of analog signal conditioning required in front of the ADC, and shifting the re-configurability of such a receiver into the digital domain as much as possible. Being closer to the antenna, and because of the increased receiver flexibility, a high performance, multi-mode ADC is required. In this thesis, it is proven that such multi-mode ADCs can be made at low area and power consumption. At analog IP architecture level, a smarter S¿ modulator architecture is found, which combines the advantages of 1-bit and multi-bit modulators. The analog loop filter is partly digitized, and analog circuit blocks are replaced by a digital filter, leading to an area and power efficient design, which above all is very portable, and has the potential to become a good candidate for the ADC in multimode receivers. At circuit and layout level, analog circuits are designed in the same way as digital circuits are. Analog IP blocks are split up in analog unit cells, which are put in a library. For each analog unit cell, a p-cell layout view is created. Once such a library is available, different IP blocks can be created using the same unit cells and using the automatic routing tools normally used for digital circuits. The library of unit cells can be ported to a next technology very quickly, as the unit cells are very simple circuits, increasing portability of IP blocks made with these unit cells. In this thesis, several modulators are presented that are designed using this digital design methodology. A high clock frequency in the giga-hertz range is used to test technology speed. The presented modulators have a small area and low power consumption. A modulator is ported from a 65nm to a 45nm technology in one month without making changes to the unit cells, or IP architecture, proving that this design methodology leads to very portable designs. The generalized system property categorization in quality indicators, and the digitization at different levels of system design, is named the digital design methodology. In this thesis this methodology is successfully applied to S¿ modulators, leading to high quality, mixed-signal S¿ modulator IP, which is more accurate, more robust, more flexible and/or more efficient
LOW POWER ANALOG-TO-DIGITAL CONVERSION CIRCUIT FOR AUDIO APPLICATION
In recent years, demand for a mixed signal LSI used for electronic equipment is increasing. High precision and low power consumption are required for ADCs for audio applications. ΔΣ ADC is a method to realize highly accurate AD conversion. However, power efficiency is poor as compared with general ADC configuration. This paper proposes a two steps ADC using a SAR-ADC and ΔΣ-ADC. The SAR-ADC arranged in the preceding stage can relax the required performance of the analog circuit of ΔΣ ADC. Therefore, low power consumption can be achieved. This proposal is designed with 0.18um CMOS. The performance of proposed system is confirmed by system simulation using MATLAB / Simulink and circuit simulation using Virtuoso / spectre, respectively
The evaluation of the instrumentation of an acoustic measurement buoy designed to monitor the underwater acoustic environment during pile driving activity
Driving large support piles in brackish estuaries results in permanent damage, and possibly death to marine mammals and fragile infant fish spawned in these areas. The damage is a result of excessive acoustic intensities produced by the pile driving activity. To monitor this \u27noise\u27, students in the Undergraduate Ocean Research Projects: TECH 797 2005-2006 (Risso et al. 2006), working with Dr. Ken Baldwin as their advisor, proposed the concept of using an \u27Acoustic Measurement Buoy\u27. Their project was funded by the National Sea Grant College Program, NOAA, and Department of Commerce.
Their problem statement was To develop a portable, robust, and inexpensive system for measurement of waterborne noise associated with construction in coastal and estuarine regions (Risso et al. 2006). Based upon extensive testing and experimentation, this thesis evaluates the feasibility of their design, the problems encountered, some solutions and recommendations for improvements in putting the \u27Acoustic Measurement Buoy\u27 to practical use. The individual components were analyzed to compare their requirements, specifications and performance.
Evaluations were performed on a test bench, in the tank in the Jere Chase Ocean Engineering Lab, on the R/V Gulf Challenger and at a floating dock in a coastal marine environment. The data were collected using National Instruments LabVIEW(TM) software, data acquisition hardware, and post processed using Matlab(TM) software. Standard techniques in failure and root cause analysis, such as cause and effect diagrams, fishbone diagrams, flow diagrams and process maps will be used in the data and component analysis
The design and implementation of a wideband digital radio receiver
Historically radio has been implemented using largely analogue circuitry. Improvements in mixed signal and digital signal processing technology are rapidly leading towards a largely digital approach, with down-conversion and filtering moving to the digital signal processing domain. Advantages of this technology include increased performance and functionality, as well as reduced cost. Wideband receivers place the heaviest demands on both mixed signal and digital signal processing technology, requiring high spurious free dynamic range (SFDR) and signal processing bandwidths. This dissertation investigates the extent to which current digital technology is able to meet these demands and compete with the proven architectures of analogue receivers. A scalable generalised digital radio receiver capable of operating in the HF and VHF bands was designed, implemented and tested, yielding instantaneous bandwidths in excess of 10 MHz with a spurious-free dynamic range exceeding 80 decibels below carrier (dBc). The results achieved reflect favourably on the digital receiver architecture. While the necessity for minimal analogue circuitry will possibly always exist, digital radio architectures are currently able to compete with analogue counterparts. The digital receiver is simple to manufacture, based on the use of largely commercial off-the-shelf (COTS) components, and exhibits extreme flexibility and high performance when compared with comparably priced analogue receivers
Linearization of Time-encoded ADCs Architectures for Smart MEMS Sensors in Low Power CMOS Technology
Mención Internacional en el título de doctorIn the last few years, the development of mobile technologies and machine learning
applications has increased the demand of MEMS-based digital microphones.
Mobile devices have several microphones enabling noise canceling, acoustic beamforming
and speech recognition. With the development of machine learning applications
the interest to integrate sensors with neural networks has increased.
This has driven the interest to develop digital microphones in nanometer CMOS
nodes where the microphone analog-front end and digital processing, potentially
including neural networks, is integrated on the same chip.
Traditionally, analog-to-digital converters (ADCs) in digital microphones have
been implemented using high order Sigma-Delta modulators. The most common
technique to implement these high order Sigma-Selta modulators is switchedcapacitor
CMOS circuits. Recently, to reduce power consumption and make them
more suitable for tasks that require always-on operation, such as keyword recognition,
switched-capacitor circuits have been improved using inverter-based operational
amplifier integrators. Alternatively, switched-capacitor based Sigma-
Delta modulators have been replaced by continuous time Sigma-Delta converters.
Nevertheless, in both implementations the input signal is voltage encoded
across the modulator, making the integration in smaller CMOS nodes more challenging
due to the reduced voltage supply.
An alternative technique consists on encoding the input signal on time (or
frequency) instead of voltage. This is what time-encoded converters do. Lately,
time-encoding converters have gained popularity as they are more suitable to
nanometer CMOS nodes than Sigma-Delta converters. Among the ones that have
drawn more interest we find voltage-controlled oscillator based ADCs (VCOADCs).
VCO-ADCs can be implemented using CMOS inverter based ring oscillators
(RO) and digital circuitry. They also show noise-shaping properties.
This makes them a very interesting alternative for implementation of ADCs in
nanometer CMOS nodes. Nevertheless, two main circuit impairments are present
in VCO-ADCs, and both come from the oscillator non-idealities. The first of them
is the oscillator phase noise, that reduces the resolution of the ADC. The second
is the non-linear tuning curve of the oscillator, that results in harmonic distortion
at medium to high input amplitudes.
In this thesis we analyze the use of time encoding ADCs for MEMS microphones
with special focus on ring oscillator based ADCs (RO-ADCs). Firstly, we
study the use of a dual-slope based SAR noise shaped quantizer (SAR-NSQ) in
sigma-delta loops. This quantizer adds and extra level of noise-shaping to the modulator, improving the resolution. The quantizer is explained, and equations
for the noise transfer function (NTF) of a third order sigma-delta using a second
order filter and the NSQ are presented.
Secondly, we move our attention to the topic of RO-ADCs. We present a high
dynamic range MEMS microphone 130nm CMOS chip based on an open-loop
VCO-ADC. This dissertation shows the implementation of the analog front-end
that includes the oscillator and the MEMS interface, with a focus on achieving
low power consumption with low noise and a high dynamic range. The digital
circuitry is left to be explained by the coauthor of the chip in his dissertation. The
chip achieves a 80dBA peak SNDR and 108dB dynamic range with a THD of 1.5%
at 128 dBSPL with a power consumption of 438μW.
After that, we analyze the use of a frequency-dependent-resistor (FDR) to implement
an unsampled feedback loop around the oscillator. The objective is to reduce
distortion. Additionally phase noise mitigation is achieved. A first topology
including an operational amplifier to increase the loop gain is analyzed. The design
is silicon proven in a 130 nm CMOS chip that achieves a 84 dBA peak SNDR
with an analog power consumption of 600μW. A second topology without the
operational amplifier is also analyzed. Two chips are designed with this topology.
The first chip in 130 nm CMOS is a full VCO-ADC including the frequencyto-
digital converter (F2D). This chip achieves a peak SNDR of 76.6 dBA with a
power consumption of 482μW. The second chip includes only the oscillator and
is implemented in 55nm CMOS. The peak SNDR is 78.15 dBA and the analog
power consumption is 153μW.
To finish this thesis, two circuits that use an FDR with a ring oscillator are
presented. The first is a capacity-to-digital converter (CDC). The second is a filter
made with an FDR and an oscillator intended for voice activity detection tasks
(VAD).En los últimos años, el desarrollo de las tecnologías móviles y las aplicaciones de
machine-learning han aumentado la demanda de micrófonos digitales basados
en MEMS. Los dipositivos móviles tienen varios micrófonos que permiten la cancelación
de ruido, el beamforming o conformación de haces y el reconocimiento
de voz. Con el desarrollo de aplicaciones de aprendizaje automático, el interés
por integrar sensores con redes neuronales ha aumentado. Esto ha impulsado el
interés por desarrollar micrófonos digitales en nodos CMOS nanométricos donde
el front-end analógico y el procesamiento digital del micrófono, que puede
incluir redes neuronales, está integrado en el mismo chip.
Tradicionalmente, los convertidores analógicos-digitales (ADC) en micrófonos
digitales han sido implementados utilizando moduladores Sigma-Delta de
orden elevado. La técnica más común para implementar estos moduladores Sigma-
Delta es el uso de circuitos CMOS de capacidades conmutadas. Recientemente,
para reducir el consumo de potencia y hacerlos más adecuados para las tareas que
requieren una operación continua, como el reconocimiento de palabras clave, los
convertidores Sigma-Delta de capacidades conmutadas has sido mejorados con
el uso de integradores implementados con amplificadores operacionales basados
en inversores CMOS. Alternativamente, los Sigma-Delta de capacidades conmutadas
han sido reemplazados por moduladores en tiempo continuo. No obstante,
en ambas implementaciones, la señal de entrada es codificada en voltaje durante
el proceso de conversión, lo que hace que la integración en nodos CMOS más
pequeños sea complicada debido a la menor tensión de alimentación.
Una técnica alternativa consiste en codificar la señal de entrada en tiempo (o
frecuencia) en lugar de tensión. Esto es lo que hacen los convertidores de codificación
temporal. Recientemente, los convertidores de codificación temporal
han ganado popularidad ya que son más adecuados para nodos CMOS nanométricos
que los convertidores Sigma-Delta. Entre los que más interés han despertado
encontramos los ADCs basados en osciladores controlados por tensión
(VCO-ADC). Los VCO-ADC se pueden implementar usando osciladores en anillo
(RO) implementados con inversores CMOS y circuitos digitales. Esta familia
de convertidores también tiene conformado de ruido. Esto los convierte en una
alternativa muy interesante para la implementación de convertidores en nodos
CMOS nanométricos. Sin embargo, dos problemas principales están presentes en
este tipo de ADCs debidos ambos a las no idealidades del oscilador. El primero
de los problemas es la presencia de ruido de fase en el oscilador, lo que reduce la resolución del ADC. El segundo es la curva de conversion voltaje-frecuencia no
lineal del oscilador, lo que causa distorsión a amplitudes medias y altas.
En esta tesis analizamos el uso de ADCs de codificación temporal para micrófonos
MEMS, con especial interés en ADCS basados en osciladores de anillo
(RO-ADC). En primer lugar, estudiamos el uso de un cuantificador SAR con conformado
de ruido (SAR-NSQ) en moduladores Sigma-Delta. Este cuantificador
agrega un orden adicional de conformado de ruido al modulador, mejorando la
resolución. En este documento se explica el cuantificador y obtienen las ecuaciones
para la función de transferencia de ruido (NTF) de un sigma-delta de tercer
orden usando un filtro de segundo orden y el NSQ.
En segundo lugar, dirigimos nuestra atención al tema de los RO-ADC. Presentamos
el chip de un micrófono MEMS de alto rango dinámico en CMOS de
130 nm basado en un VCO-ADC de bucle abierto. En esta tesis se explica la implementación
del front-end analógico que incluye el oscilador y la interfaz con
el MEMS. Esta implementación se ha llevado a cabo con el objetivo de lograr un
bajo consumo de potencia, un bajo nivel de ruido y un alto rango dinámico. La
descripción del back-end digital se deja para la tesis del couator del chip. La
SNDR de pico del chip es de 80dBA y el rango dinámico de 108dB con una THD
de 1,5% a 128 dBSPL y un consumo de potencia de 438μW.
Finalmente, se analiza el uso de una resistencia dependiente de frecuencia
(FDR) para implementar un bucle de realimentación no muestreado alrededor
del oscilador. El objetivo es reducir la distorsión. Además, también se logra la
mitigación del ruido de fase del oscilador. Se analyza una primera topologia de
realimentación incluyendo un amplificador operacional para incrementar la ganancia
de bucle. Este diseño se prueba en silicio en un chip CMOS de 130nm que
logra un pico de SNDR de 84 dBA con un consumo de potencia de 600μW en la
parte analógica. Seguidamente, se analiza una segunda topología sin el amplificador
operacional. Se fabrican y miden dos chips diseñados con esta topologia.
El primero de ellos en CMOS de 130 nm es un VCO-ADC completo que incluye
el convertidor de frecuencia a digital (F2D). Este chip alcanza un pico SNDR de
76,6 dBA con un consumo de potencia de 482μW. El segundo incluye solo el oscilador
y está implementado en CMOS de 55nm. El pico SNDR es 78.15 dBA y el
el consumo de potencia analógica es de 153μW.
Para cerrar esta tesis, se presentan dos circuitos que usan la FDR con un oscilador
en anillo. El primero es un convertidor de capacidad a digital (CDC). El
segundo es un filtro realizado con una FDR y un oscilador, enfocado a tareas de
detección de voz (VAD).Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Antonio Jesús Torralba Silgado.- Secretaria: María Luisa López Vallejo.- Vocal: Pieter Rombout
Data acquisition techniques based on frequency-encoding applied to capacitive MEMS microphones
Mención Internacional en el título de doctorThis thesis focuses on the development of capacitive sensor readout circuits
and data converters based on frequency-encoding. This research
has been motivated by the needs of consumer electronics industry, which
constantly demands more compact readout circuit for MEMS microphones
and other sensors. Nowadays, data acquisition is mainly based
on encoding signals in voltage or current domains, which is becoming
more challenging in modern deep submicron CMOS technologies.
Frequency-encoding is an emerging signal processing technique based
on encoding signals in the frequency domain. The key advantage of
this approach is that systems can be implemented using mostly-digital
circuitry, which benefits from CMOS technology scaling. Frequencyencoding
can be used to build phase referenced integrators, which can
replace classical integrators (such as switched-capacitor based integrators)
in the implementation of efficient analog-to-digital converters and
sensor interfaces. The core of the phase referenced integrators studied in
this thesis consists of the combination of different oscillator topologies
with counters and highly-digital circuitry.
This work addresses two related problems: the development of capacitive
MEMS sensor readout circuits based on frequency-encoding, and the
design and implementation of compact oscillator-based data converters
for audio applications.
In the first problem, the target is the integration of the MEMS sensor
into an oscillator circuit, making the oscillation frequency dependent on
the sensor capacitance. This way, the sound can be digitized by measuring
the oscillation frequency, using digital circuitry. However, a MEMS
microphone is a complex structure on which several parasitic effects can
influence the operation of the oscillator. This work presents a feasibility
analysis of the integration of a MEMS microphone into different oscillator
topologies. The conclusion of this study is that the parasitics of the
MEMS limit the performance of the microphone, making it inefficient.
In contrast, replacing conventional ADCs with frequency-encoding based
ADCs has proven a very efficient solution, which motivates the next
problem.
In the second problem, the focus is on the development of high-order
oscillator-based Sigma-Delta modulators. Firstly, the equivalence between classical
integrators and phase referenced integrators has been studied, followed
by an overview of state-of-art oscillator-based converters. Then,
a procedure to replace classical integrators by phase referenced integrators
is presented, including a design example of a second-order oscillator based
Sigma-Delta modulator. Subsequently, the main circuit impairments that
limit the performance of this kind of implementations, such as phase
noise, jitter or metastability, are described.
This thesis also presents a methodology to evaluate the impact of
phase noise and distortion in oscillator-based systems. The proposed
method is based on periodic steady-state analysis, which allows the rapid
estimation of the system dynamic range without resorting to transient
simulations. In addition, a novel technique to analyze the impact of
clock jitter in Sigma-Delta modulators is described.
Two integrated circuits have been implemented in 0.13 μm CMOS
technology to demonstrate the feasibility of high-order oscillator-based Sigma-Delta modulators. Both chips have been designed to feature secondorder
noise shaping using only oscillators and digital circuitry. The first
testchip shows a malfunction in the digital circuitry due to the complexity
of the multi-bit counters. The second chip, implemented using
single-bit counters for simplicity, shows second-order noise shaping and
reaches 103 dB-A of dynamic range in the audio bandwidth, occupying
only 0.04 mm2.Esta tesis se centra en el desarrollo de conversores de datos e interfaces
para sensores capacitivos basados en codificación en frecuencia. Esta
investigación está motivada por las necesidades de la industria, que constantemente
demanda reducir el tamaño de este tipo de circuitos. Hoy en
día, la adquisición de datos está basada principalmente en la codificación
de señales en tensión o en corriente. Sin embargo, la implementación
de este tipo de soluciones en tecnologías CMOS nanométricas presenta
varias dificultades.
La codificación de frecuencia es una técnica emergente en el procesado
de señales basada en codificar señales en el dominio de la frecuencia.
La principal ventaja de esta alternativa es que los sistemas pueden implementarse
usando circuitos mayoritariamente digitales, los cuales se
benefician de los avances de la tecnología CMOS. La codificación en
frecuencia puede emplearse para construir integradores referidos a la
fase, que pueden reemplazar a los integradores clásicos (como los basados
en capacidades conmutadas) en la implementación de conversores
analógico-digital e interfaces de sensores. Los integradores referidos a la
fase estudiados en esta tesis consisten en la combinación de diferentes
topologías de osciladores con contadores y circuitos principalmente digitales.
Este trabajo aborda dos cuestiones relacionadas: el desarrollo de circuitos
de lectura para sensores MEMS capacitivos basados en codificación
temporal, y el diseño e implementación de conversores de datos
compactos para aplicaciones de audio basados en osciladores.
En el primer caso, el objetivo es la integración de un sensor MEMS
en un oscilador, haciendo que la frecuencia de oscilación depe capacidad del sensor. De esta forma, el sonido puede ser digitalizado
midiendo la frecuencia de oscilación, lo cual puede realizarse usando circuitos
en su mayor parte digitales. Sin embargo, un micrófono MEMS es
una estructura compleja en la que múltiples efectos parasíticos pueden
alterar el correcto funcionamiento del oscilador. Este trabajo presenta
un análisis de la viabilidad de integrar un micrófono MEMS en diferentes
topologías de oscilador. La conclusión de este estudio es que los parasíticos
del MEMS limitan el rendimiento del micrófono, causando que esta
solución no sea eficiente. En cambio, la implementación de conversores
analógico-digitales basados en codificación en frecuencia ha demostrado
ser una alternativa muy eficiente, lo cual motiva el estudio del siguiente
problema.
La segunda cuestión está centrada en el desarrollo de moduladores Sigma-Delta de alto orden basados en osciladores. En primer lugar se ha estudiado
la equivalencia entre los integradores clásicos y los integradores
referidos a la fase, seguido de una descripción de los conversores basados
en osciladores publicados en los últimos años. A continuación se
presenta un procedimiento para reemplazar integradores clásicos por integradores
referidos a la fase, incluyendo un ejemplo de diseño de un
modulador Sigma-Delta de segundo orden basado en osciladores. Posteriormente
se describen los principales problemas que limitan el rendimiento de este
tipo de sistemas, como el ruido de fase, el jitter o la metaestabilidad.
Esta tesis también presenta un nuevo método para evaluar el impacto
del ruido de fase y de la distorsión en sistemas basados en osciladores. El
método propuesto está basado en simulaciones PSS, las cuales permiten
la rápida estimación del rango dinámico del sistema sin necesidad de
recurrir a simulaciones temporales. Además, este trabajo describe una
nueva técnica para analizar el impacto del jitter de reloj en moduladores Sigma-Delta.
En esta tesis se han implementado dos circuitos integrados en tecnología
CMOS de 0.13 μm, con el fin de demostrar la viabilidad de los
moduladores Sigma-Delta de alto orden basados en osciladores. Ambos chips han
sido diseñados para producir conformación espectral de ruido de segundo
orden, usando únicamente osciladores y circuitos mayoritariamente digitales.
El primer chip ha mostrado un error en el funcionamiento de los
circuitos digitales debido a la complejidad de las estructuras multi-bit
utilizadas. El segundo chip, implementado usando contadores de un solo
bit con el fin de simplificar el sistema, consigue conformación espectral
de ruido de segundo orden y alcanza 103 dB-A de rango dinámico en el
ancho de banda del audio, ocupando solo 0.04 mm2.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Georges G.E. Gielen.- Secretario: José Manuel de la Rosa.- Vocal: Ana Rus
- …