A robust ultra-low voltage CPU utilizing timing-error prevention

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing.</p

Power efficient and power attacks resistant system design and analysis using aggressive scaling with timing speculation

Growing usage of smart and portable electronic devices demands embedded system designers to provide solutions with better performance and reduced power consumption. Due to the new development of IoT and embedded systems usage, not only power and performance of these devices but also security of them is becoming an important design constraint. In this work, a novel aggressive scaling based on timing speculation is proposed to overcome the drawbacks of traditional DVFS and provide security from power analysis attacks at the same time. Dynamic voltage and frequency scaling (DVFS) is proven to be the most suitable technique for power efficiency in processor designs. Due to its promising benefits, the technique is still getting researchers attention to trade off power and performance of modern processor designs. The issues of traditional DVFS are: 1) Due to its pre-calculated operating points, the system is not able to suit to modern process variations. 2) Since Process Voltage and Temperature (PVT) variations are not considered, large timing margins are added to guarantee a safe operation in the presence of variations. The research work presented here addresses these issues by employing aggressive scaling mechanisms to achieve more power savings with increased performance. This approach uses in-situ timing error monitoring and recovering mechanisms to reduce extra timing margins and to account for process variations. A novel timing error detection and correction mechanism, to achieve more power savings or high performance, is presented. This novel technique has also been shown to improve security of processors against differential power analysis attacks technique. Differential power analysis attacks can extract secret information from embedded systems without knowing much details about the internal architecture of the device. Simulated and experimental data show that the novel technique can provide a performance improvement of 24% or power savings of 44% while occupying less area and power overhead. Overall, the proposed aggressive scaling technique provides an improvement in power consumption and performance while increasing the security of processors from power analysis attacks.N/

Designing energy-efficient sub-threshold logic circuits using equalization and non-volatile memory circuits using memristors

The very large scale integration (VLSI) community has utilized aggressive complementary metal-oxide semiconductor (CMOS) technology scaling to meet the ever-increasing performance requirements of computing systems. However, as we enter the nanoscale regime, the prevalent process variation effects degrade the CMOS device reliability. Hence, it is increasingly essential to explore emerging technologies which are compatible with the conventional CMOS process for designing highly-dense memory/logic circuits. Memristor technology is being explored as a potential candidate in designing non-volatile memory arrays and logic circuits with high density, low latency and small energy consumption. In this thesis, we present the detailed functionality of multi-bit 1-Transistor 1-memRistor (1T1R) cell-based memory arrays. We present the performance and energy models for an individual 1T1R memory cell and the memory array as a whole. We have considered TiO2- and HfOx-based memristors, and for these technologies there is a sub-10% difference between energy and performance computed using our models and HSPICE simulations. Using a performance-driven design approach, the energy-optimized TiO2-based RRAM array consumes the least write energy (4.06 pJ/bit) and read energy (188 fJ/bit) when storing 3 bits/cell for 100 nsec write and 1 nsec read access times. Similarly, HfOx-based RRAM array consumes the least write energy (365 fJ/bit) and read energy (173 fJ/bit) when storing 3 bits/cell for 1 nsec write and 200 nsec read access times. On the logic side, we investigate the use of equalization techniques to improve the energy efficiency of digital sequential logic circuits in sub-threshold regime. We first propose the use of a variable threshold feedback equalizer circuit with combinational logic blocks to mitigate the timing errors in digital logic designed in sub-threshold regime. This mitigation of timing errors can be leveraged to reduce the dominant leakage energy by scaling supply voltage or decreasing the propagation delay. At the fixed supply voltage, we can decrease the propagation delay of the critical path in a combinational logic block using equalizer circuits and, correspondingly decrease the leakage energy consumption. For a 8-bit carry lookahead adder designed in UMC 130 nm process, the operating frequency can be increased by 22.87% (on average), while reducing the leakage energy by 22.6% (on average) in the sub-threshold regime. Overall, the feedback equalization technique provides up to 35.4% lower energy-delay product compared to the conventional non-equalized logic. We also propose a tunable adaptive feedback equalizer circuit that can be used with sequential digital logic to mitigate the process variation effects and reduce the dominant leakage energy component in sub-threshold digital logic circuits. For a 64-bit adder designed in 130 nm our proposed approach can reduce the normalized delay variation of the critical path delay from 16.1% to 11.4% while reducing the energy-delay product by 25.83% at minimum energy supply voltage. In addition, we present detailed energy-performance models of the adaptive feedback equalizer circuit. This work serves as a foundation for the design of robust, energy-efficient digital logic circuits in sub-threshold regime

Exploiting robustness in asynchronous circuits to design fine-tunable systems

PhD ThesisRobustness property in a circuit defines its tolerance to the effects of process, voltage and temperature variations. The mode signaling and event communication between computing units in a asynchronous circuits makes them inherently robust. The level of robustness depends on the type of delay assumptions used in the design and specification process. In this thesis, two approaches to exploiting robustness in asynchronous circuits to design self-adapting and fine-tunable systems are investigated. In the first investigation, a Digitally Controllable Oscillator (DCO) and a computing unit are integrated such that the operating conditions of the computing unit modulated the operation of the DCO. In this investigation, the computing unit which is a self-timed counter interacts with the DCO in a four-phase handshake protocol. This mode of interaction ensures a DCO and computing unit system that can fine-tune its operation to adapt to the effects of variations. In this investigation, it is shown that such a system will operate correctly in wide range of voltage supply. In the second investigation, a Digital Pulse-Width Modulator (DPWM) with coarse and fine-tune controls is designed using two Kessels counters. The coarse control of the DPWM tuned the pulse ratio and pulse frequency while the fine-tune control exploited the robustness property of asynchronous circuits in an addition-based delay system to add or subtract delay(s) to the pulse width while maintaining a constant pulse frequency. The DPWM realized gave constant duty ratio regardless of the operating voltage. This type of DPWM has practical application in a DC-DC converter circuit to tune the output voltage of the converter in high resolution. The Kessels counter is a loadable self-timed modulo−n counter, which is realized by decomposition using Horner’s method, specified and verified using formal asynchronous design techniques. The decomposition method used introduced parallelism in the system by dividing the counter into a systolic array of cells, with each cell further decomposed into two parts that have distinct defined operations. Specification of the decomposed counter cell parts operation was in three stages. The first stage employed high-level specification using Labelled Petri nets (LPN). In this form, functional correctness of the decomposed counter is modelled and verified. In the second stage, a cell part is specified by combing all possible operations for that cell part in high-level form. With this approach, a combination of inputs from a defined control block activated the correct operation for a cell part. In the final stage, the LPNs were converted to Signal Transition Graphs, from which the logic circuits of the cells were synthesized using the WorkCraft Tool. In this thesis, the Kessels counter was implemented and fabricated in 350 nm CMOS Technology.Niger Delta Development Commission (NDD

Safety and Reliability - Safe Societies in a Changing World

The contributions cover a wide range of methodologies and application areas for safety and reliability that contribute to safe societies in a changing world. These methodologies and applications include: - foundations of risk and reliability assessment and management - mathematical methods in reliability and safety - risk assessment - risk management - system reliability - uncertainty analysis - digitalization and big data - prognostics and system health management - occupational safety - accident and incident modeling - maintenance modeling and applications - simulation for safety and reliability analysis - dynamic risk and barrier management - organizational factors and safety culture - human factors and human reliability - resilience engineering - structural reliability - natural hazards - security - economic analysis in risk managemen

The relevance of non-legal technical and scientific concepts in the interpretation and application of the law of the sea : an analysis of the United Nations convention on the law of the sea

Bibliography: p. 363-375.Of necessity LOSC Articles are brief and in some instances vague and requiring interpretation. There is general consensus that LOSC is successful and that its vagueness in certain areas is an asset allowing a variety of otherwise contrary attitudes to be accommodated. 1 It is necessary to analyse the Articles with a view to a better understanding of them and to possibly prepare for some future conference or convention that will more than likely be necessary to resolve some of the remaining problems. To illustrate the need for greater understanding of some of the Articles of LOSC the United Nations Office for Ocean Affairs and Law of the Sea found it necessary to convene a conference of 'experts' during 1993 and 1995 to consider the implications of the complex Articles of LOSC which deal with claims to the continental shelf. Criteria contained in Article 76 allowing for maximum outer limits of the continental shelf and other criteria to justify a claim are complicated and require experience in many fields including marine geology, geography, surveying, and geodesy.2 The intention is therefore to analyse the possible interpretation, application and consequences of the implementation of Articles in LOSC, and more particularly in a Southern African context. Provisions of LOSC, where technical and scientific considerations are crucial, will be selected for consideration. These include those involving geodetic, geographical, geological, survey, navigational, organisational, and social and resource factors

Estimating the impact of interventions on viral epidemics using epidemiological and evolutionary models

Mathematical modelling is useful for understanding infectious disease epidemics, and for estimating the impact of interventions to control them. However, the appropriateness of different modelling approaches depends on the local context and availability of data. In this thesis I use two approaches, epidemiological and evolutionary modelling, to estimate the impact of interventions for controlling HIV and COVID-19. After developing a dynamic transmission model fitted to local demographic, HIV prevalence and antiretroviral therapy (ART) coverage data, I estimated the impact of a 2-year real-world demonstration study of pre-exposure prophylaxis (PrEP) and ART treatment-as-prevention (TasP) among female sex workers (FSW) in Cotonou, Benin. I further estimated the impact of long-term scale-up scenarios of PrEP and TasP among FSW in Cotonou. Next, based on data collected during the 2020 COVID-19 epidemic in Benin, I simulated scenarios of COVID-related disruptions to HIV services and sexual behaviour, using the same dynamic transmission model. I estimated the impact of these disruptions on HIV epidemiology in Cotonou. Many non-pharmaceutical interventions (NPIs), including travel restrictions and lockdowns, were implemented globally to control COVID-19. Using model-based phylodynamic methods fitted to twenty SARS-CoV-2 genomes, I estimated the impact of NPIs in Weifang, China, one of the first COVID-19 epidemics outside of Wuhan. Finally, I performed several non-parametric phylodynamic analyses on the COVID-19 epidemic in England, fitted to thousands of SARS-CoV-2 genomes. I evaluated the association of stringency of NPIs and mobility with viral transmission at different periods between spring 2020 and winter 2020-2021. I further investigated the relative growth rates between different viral lineages, including the B.1.1.7 (’alpha’) variant. The results from this thesis are useful principally to policymakers for designing effective local control measures for HIV and COVID-19. While modelling can be used to estimate the impact of interventions, model choice must be tailored to the local epidemiological context.Open Acces

The decisive reset: attainable governance for revitalising democracy

To improve democratic legitimacy, successful resolution of public policy challenges has to emerge from highly pressurised political predicaments. Increasing civic functionality requires integrative Civil Service practice, building trust in adaptive oversight. With the task of effective governance stretching out-of-reach in straining institutional arrangements, a proposition is developed for an “Attainable Governance” reset to revitalise democracy. Motivated by the need for progress that is sensitive to the reality and risks of the present and embodying requirements to hold open unforeseen possibilities for future action, the groundwork is laid for a new “decision architecture” that improves policy-framing and decision-making. With a mission to compose a conceptual framework for “facing the future” in the United Kingdom, I make the case for refreshing democratic arrangements, including a proposed structural intervention to the policy-making system with a correlative cultural step-change in leadership. Laying out a novel framework, the analysis draws widely on strands of thinking in social theory and political philosophy, public administration and policy-making, systems thinking and design, planning and strategic management, anticipation and futures, economics, and sociology. Taking an “integral” methodological orientation, in three parts I: (1) diagnose the converging Predicament, (2) develop a conceptual Proposition, and 3) sketch-out an approach to leadership that facilitates operational adaption in Procedures for applied practice. Positing that we have to deal with systems-of-problems (“messes”) and system-of-systems (“systemic messes”) with an analytic primacy on expanding temporal considerations to factor in more anticipative insights, I take a Complex Adaptive Systems-informed stance. The need for a “Decisive Reset” to refresh democracy, featuring phased systemic reordering and tactical modularity to produce better public decision-making that is responsive and agile in the short-run, while actively gauging medium-term realities and future-proofing for long-run uncertainties, results in a new decision architecture and methodology

Internet of Things From Hype to Reality

The Internet of Things (IoT) has gained significant mindshare, let alone attention, in academia and the industry especially over the past few years. The reasons behind this interest are the potential capabilities that IoT promises to offer. On the personal level, it paints a picture of a future world where all the things in our ambient environment are connected to the Internet and seamlessly communicate with each other to operate intelligently. The ultimate goal is to enable objects around us to efficiently sense our surroundings, inexpensively communicate, and ultimately create a better environment for us: one where everyday objects act based on what we need and like without explicit instructions