Advanced CMOS Integrated Circuit Design and Application

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

Novel High Performance Ultra Low Power Static Random Access Memories (SRAMs) Based on Next Generation Technologies

Title from PDF of title page viewed January 27, 2021Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (page 107-120)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2019Next Big Thing Is Surely Small: Nanotechnology Can Bring Revolution. Nanotechnology leads the world towards many new applications in various fields of computing, communication, defense, entertainment, medical, renewable energy and environment. These nanotechnology applications require an energy-efficient memory system to compute and process. Among all the memories, Static Random Access Memories (SRAMs) are high performance memories and occupies more than 50% of any design area. Therefore, it is critical to design high performance and energy-efficient SRAM design. Ultra low power and high speed applications require a new generation memory capable of operating at low power as well as low execution time. In this thesis, a novel 8T SRAM design is proposed that offers significantly faster access time and lowers energy consumption along with better read stability and write ability. The proposed design can be used in the conventional SRAM as well as in computationally intensive applications like neural networks and machine learning classifiers [1]-[4]. Novel 8T SRAM design offers higher energy efficiency, reliability, robustness and performance compared to the standard 6T and other existing 8T and 9T designs. It offers the advantages of a 10T SRAM without the additional area, delay and power overheads of the 10T SRAM. The proposed 8T SRAM would be able to overcome many other limitations of the conventional 6T and other 7T, 8T and 9T designs. The design employs single bitline for the write operation, therefore the number of write drivers are reduced. The defining feature of the proposed 8T SRAM is its hybrid design, which is the combination of two techniques: (i) the utilization of single-ended bitline and (ii) the utilization of virtual ground. The single-ended bitline technique ensures separate read and write operations, which eventually reduces the delay and power consumption during the read and write operations. It's independent read and write paths allow the use of the minimum sized access transistors and aid in a disturb-free read operation. The virtual ground weakens the positive feedback in the SRAM cell and improves its write ability. The virtual ground technique is also used to reduce leakages. The proposed design does not require precharging the bitlines for the read operation, which reduces the area and power overheads of the memory system by eliminating the precharging circuit. The design isolates the storage node from the read path, which improves the read stability. For reliability study, we have investigated the static noise margin (SNM) of the proposed 8T SRAM, for which, we have used two methods – (i) the traditional SNM method with the butterfly curve, (ii) the N-curve method A comparative analysis is performed between the proposed and the existing SRAM designs in terms of area, total power consumption during the read and write operations, and stability and reliability. All these advantages make the proposed 8T SRAM design an ideal candidate for the conventional and computationally intensive applications like machine learning classifier and deep learning neural network. In addition to this, there is need for next generation technologies to design SRAM memory because the conventional CMOS technology is approaching its physical and performance boundaries and as a consequence, becoming incompatible with ultra-low-power applications. Emerging devices such as Tunnel Field Effect Transistor (TFET)) and Graphene Nanoribbon Field Effect Transistor (GNRFET) devices are highly potential candidates to overcome the limitations of MOSFET because of their ability to achieve subthreshold slopes below 60 mV/decade and very low leakage currents [6]-[9]. This research also explores novel TFET and GNRFET based 6T SRAM. The thesis evaluates the standby leakage power in the Tunnel FET (TFET) based 6T SRAM cell for different pull-up, pull-down, and pass-gate transistors ratios (PU: PD: PG) and compared to 10nm FinFET based 6T SRAM designs. It is observed that the 10nm TFET based SRAMs have 107.57%, 163.64%, and 140.44% less standby leakage power compared to the 10nm FinFET based SRAMs when the PU: PD: PG ratios are 1:1:1, 1:5:2 and 2:5:2, respectively. The thesis also presents an analysis of the stability and reliability of sub-10nm TFET based 6T SRAM circuit with a reduced supply voltage of 500mV. The static noise margin (SNM), which is a critical measure of SRAM stability and reliability, is determined for hold, read and write operations of the 6T TFET SRAM cell. The robustness of the optimized TFET based 6T SRAM circuit is also evaluated at different supply voltages. Simulations were done in HSPICE and Cadence tools. From the analysis, it is clear that the main advantage of the TFET based SRAM would be the significant improvement in terms of leakage or standby power consumption. Compared to the FinFET based SRAM the standby leakage power of the T-SRAMs are 107.57%, 163.64%, and 140.44% less for 1:1:1, 1:5:2 and 2:5:2 configurations, respectively. Since leakage/standby power is the primary source of power consumption in the SRAM, and the overall system energy efficiency depends on SRAM power consumption, TFET based SRAM would lead to massive improvement of the energy efficiency of the system. Therefore, T-SRAMs are more suitable for ultra-low power applications. In addition to this, the thesis evaluates the standby leakage power of types of Graphene Nanoribbon FETs based 6T SRAM bitcell and compared to 10nm FinFET based 6T SRAM bitcell. It is observed that the 10nm MOS type GNRFET based SRAMs have 16.43 times less standby leakage power compared to the 10nm FinFET based SRAMs. The double gate SB-GNRFET based SRAM consumes 1.35E+03 times less energy compared to the 10nm FinFET based SRAM during write. However, during read double gate SB-GNRFET based SRAM consume 15 times more energy than FinFET based SRAM. It is also observed that GNRFET based SRAMs are more stable and reliable than FinFET based SRAM.Introduction -- Background -- Novel High Performance Ultra Low Power SRAM Design -- Tunnel FET Based SRAM Design -- Graphene Nanoribbon FET Based SRAM Design -- Double-gate FDSOI Based SRAM Designs -- Novel CNTFET and MEMRISTOR Based Digital Designs -- Conclusio

Application of memristors in realization of microwave passive circuits

Предмет истраживања ове докторске дисертације је примјена мемристора у реализацији планарних микроталасних пасивних кола. У фокусу истраживања је микроталасни помјерач фазе остварен коришћењем мемристивних прекидача. Истраживање обухвата и реализацију микроталасних филтара са мемристорима. Циљ истраживања је реализација микроталасног помјерача фазе који има боље карактеристике у односу на карактеристике одговарајућих помјерача фазе објављених у доступној отвореној литератури, а који користе традиционалне прекидаче као што су PIN диоде, микроелектромеханички прекидачи и CMOS. Такође, циљ истраживања представља и анализа могућих реализација микроталасних филтара коришћењем мемристора. Доприноси дисертације су нов метод пројектовања помјерача фазе, коришћењем мемристора, а којим се смањује потрошња уређаја и поправља константност фазног помјераја у специфицираном фреквенцијском опсегу. При реализацији филтара, коришћењем мемристора потиснути су нежељени пропусни опсези, реализован је реконфигурабилни филтар коришћењем мемристивних прекидача. Поред тога, пројектован је хардвер за аутоматско програмирање комерцијално доступног мемристора компаније KnowM, развијен је алгоритам и софтвер микроконтролера који омогућава аутоматско програмирање, као и софтвер преносивог или удаљеног уређаја за контролу рада микроконтролера. Пројектована су електрична кола остварена коришћењем комерцијално доступног мемристора. Предложен је модел за фреквенцијску анализу комерцијално доступног мемристора на учестаностима до 1 MHz. Пројектован је активни филтар пропусник опсега, који има могућност подешавања централне фреквенције при радном режиму. За експерименталну верификацију рада програматора и електричних кола направљени су лабораторијски прототипови.The scope of the research presented in this doctoral dissertation is the application of memristors in the realization of planar microwave passive circuits. The focus of the research was the microwave phase shifter realized using memristive switches. In addition, the research includes the realization of microwave filters by incorporating memristors. The aim of the research is the realization of a microwave phase shifter with better characteristics compared to the characteristics of phase shifters available in the open literature, which use traditional switches like PIN diodes, microelectromechanical systems, and CMOS. Also, the aim of the research is the analysis of microwave filters with incorporated memristors. The contribution of the doctoral dissertation is a novel method of designing microwave phase shifters - by using memristors which reduces the power consumption of the device and improves the constancy of the phase shift in the specified frequency range. By using memristors in the realization of filters, unwanted bandwidths are suppressed, and a reconfigurable filter is realized by using memristive switches. In addition, hardware for the automatic programming of KnowM's commercially available memristors has been designed, an algorithm and microcontroller software that enables automatic programming have been developed, as well as software for a portable or remote device to control the operation of the microcontroller. Electrical circuits designed using the commercially available memristor were realized. A frequency analysis model of the commercially available memristor at frequencies of up to 1 MHz has been proposed. An active bandpass filter has been designed, which has the ability to tune the center frequency during operation. Laboratory prototypes were made for the experimental verification of the operation of programmers and electrical circuits

Robust Design With Increasing Device Variability In Sub-Micron Cmos And Beyond: A Bottom-Up Framework

My Ph.D. research develops a tiered systematic framework for designing process-independent and variability-tolerant integrated circuits. This bottom-up approach starts from designing self-compensated circuits as accurate building blocks, and moves up to sub-systems with negative feedback loop and full system-level calibration. a. Design methodology for self-compensated circuits My collaborators and I proposed a novel design methodology that offers designers intuitive insights to create new topologies that are self-compensated and intrinsically process-independent without external reference. It is the first systematic approaches to create "correct-by-design" low variation circuits, and can scale beyond sub-micron CMOS nodes and extend to emerging non-silicon nano-devices. We demonstrated this methodology with an addition-based current source in both 180nm and 90nm CMOS that has 2.5x improved process variation and 6.7x improved temperature sensitivity, and a GHz ring oscillator (RO) in 90nm CMOS with 65% reduction in frequency variation and 85ppm/oC temperature sensitivity. Compared to previous designs, our RO exhibits the lowest temperature sensitivity and process variation, while consuming the least amount of power in the GHz range. Another self-compensated low noise amplifiers (LNA) we designed also exhibits 3.5x improvement in both process and temperature variation and enhanced supply voltage regulation. As part of the efforts to improve the accuracy of the building blocks, I also demonstrated experimentally that due to "diversification effect", the upper bound of circuit accuracy can be better than the minimum tolerance of on-chip devices (MOSFET, R, C, and L), which allows circuit designers to achieve better accuracy with less chip area and power consumption. b. Negative feedback loop based sub-system I explored the feasibility of using high-accuracy DC blocks as low-variation "rulers-on-chip" to regulate high-speed high-variation blocks (e.g. GHz oscillators). In this way, the trade-off between speed (which can be translated to power) and variation can be effectively de-coupled. I demonstrated this proposed structure in an integrated GHz ring oscillators that achieve 2.6% frequency accuracy and 5x improved temperature sensitivity in 90nm CMOS. c. Power-efficient system-level calibration To enable full system-level calibration and further reduce power consumption in active feedback loops, I implemented a successive-approximation-based calibration scheme in a tunable GHz VCO for low power impulse radio in 65nm CMOS. Events such as power-up and temperature drifts are monitored by the circuits and used to trigger the need-based frequency calibration. With my proposed scheme and circuitry, the calibration can be performed under 135pJ and the oscillator can operate between 0.8 and 2GHz at merely 40[MICRO SIGN]W, which is ideal for extremely power-and-cost constraint applications such as implantable biomedical device and wireless sensor networks

18th IEEE Workshop on Nonlinear Dynamics of Electronic Systems: Proceedings

Proceedings of the 18th IEEE Workshop on Nonlinear Dynamics of Electronic Systems, which took place in Dresden, Germany, 26 – 28 May 2010.:Welcome Address ........................ Page I Table of Contents ........................ Page III Symposium Committees .............. Page IV Special Thanks ............................. Page V Conference program (incl. page numbers of papers) ................... Page VI Conference papers Invited talks ................................ Page 1 Regular Papers ........................... Page 14 Wednesday, May 26th, 2010 ......... Page 15 Thursday, May 27th, 2010 .......... Page 110 Friday, May 28th, 2010 ............... Page 210 Author index ............................... Page XII

MEMS Technology for Biomedical Imaging Applications

Biomedical imaging is the key technique and process to create informative images of the human body or other organic structures for clinical purposes or medical science. Micro-electro-mechanical systems (MEMS) technology has demonstrated enormous potential in biomedical imaging applications due to its outstanding advantages of, for instance, miniaturization, high speed, higher resolution, and convenience of batch fabrication. There are many advancements and breakthroughs developing in the academic community, and there are a few challenges raised accordingly upon the designs, structures, fabrication, integration, and applications of MEMS for all kinds of biomedical imaging. This Special Issue aims to collate and showcase research papers, short commutations, perspectives, and insightful review articles from esteemed colleagues that demonstrate: (1) original works on the topic of MEMS components or devices based on various kinds of mechanisms for biomedical imaging; and (2) new developments and potentials of applying MEMS technology of any kind in biomedical imaging. The objective of this special session is to provide insightful information regarding the technological advancements for the researchers in the community

Inorganic micro/nanostructures-based high-performance flexible electronics for electronic skin application

Electronics in the future will be printed on diverse substrates, benefiting several emerging applications such as electronic skin (e-skin) for robotics/prosthetics, flexible displays, flexible/conformable biosensors, large area electronics, and implantable devices. For such applications, electronics based on inorganic micro/nanostructures (IMNSs) from high mobility materials such as single crystal silicon and compound semiconductors in the form of ultrathin chips, membranes, nanoribbons (NRs), nanowires (NWs) etc., offer promising high-performance solutions compared to conventional organic materials. This thesis presents an investigation of the various forms of IMNSs for high-performance electronics. Active components (from Silicon) and sensor components (from indium tin oxide (ITO), vanadium pentaoxide (V2O5), and zinc oxide (ZnO)) were realised based on the IMNS for application in artificial tactile skin for prosthetics/robotics. Inspired by human tactile sensing, a capacitive-piezoelectric tandem architecture was realised with indium tin oxide (ITO) on a flexible polymer sheet for achieving static (upto 0.25 kPa-1 sensitivity) and dynamic (2.28 kPa-1 sensitivity) tactile sensing. These passive tactile sensors were interfaced in extended gate mode with flexible high-performance metal oxide semiconductor field effect transistors (MOSFETs) fabricated through a scalable process. The developed process enabled wafer scale transfer of ultrathin chips (UTCs) of silicon with various devices (ultrathin chip resistive samples, metal oxide semiconductor (MOS) capacitors and n‐channel MOSFETs) on flexible substrates up to 4″ diameter. The devices were capable of bending upto 1.437 mm radius of curvature and exhibited surface mobility above 330 cm2/V-s, on-to-off current ratios above 4.32 decades, and a subthreshold slope above 0.98 V/decade, under various bending conditions. While UTCs are useful for realizing high-density high-performance micro-electronics on small areas, high-performance electronics on large area flexible substrates along with low-cost fabrication techniques are also important for realizing e-skin. In this regard, two other IMNS forms are investigated in this thesis, namely, NWs and NRs. The controlled selective source/drain doping needed to obtain transistors from such structure remains a bottleneck during post transfer printing. An attractive solution to address this challenge based on junctionless FETs (JLFETs), is investigated in this thesis via technology computer-aided design (TCAD) simulation and practical fabrication. The TCAD optimization implies a current of 3.36 mA for a 15 μm channel length, 40 μm channel width with an on-to-off ratio of 4.02x 107. Similar to the NRs, NWs are also suitable for realizing high performance e-skin. NWs of various sizes, distribution and length have been fabricated using various nano-patterning methods followed by metal assisted chemical etching (MACE). Synthesis of Si NWs of diameter as low as 10 nm and of aspect ratio more than 200:1 was achieved. Apart from Si NWs, V2O5 and ZnO NWs were also explored for sensor applications. Two approaches were investigated for printing NWs on flexible substrates namely (i) contact printing and (ii) large-area dielectrophoresis (DEP) assisted transfer printing. Both approaches were used to realize electronic layers with high NW density. The former approach resulted in 7 NWs/μm for bottom-up ZnO and 3 NWs/μm for top-down Si NWs while the latter approach resulted in 7 NWs/μm with simultaneous assembly on 30x30 electrode patterns in a 3 cm x 3 cm area. The contact-printing system was used to fabricate ZnO and Si NW-based ultraviolet (UV) photodetectors (PDs) with a Wheatstone bridge (WB) configuration. The assembled V2O5 NWs were used to realize temperature sensors with sensitivity of 0.03% /K. The sensor arrays are suitable for tactile e-skin application. While the above focuses on realizing conventional sensing and addressing elements for e-skin, processing of a large amount of data from e-skin has remained a challenge, especially in the case of large area skin. A Neural NW Field Effect Transistors (υ-NWFETs) based hardware-implementable neural network (HNN) approach for tactile data processing in e-skin is presented in the final part of this thesis. The concept is evaluated by interfacing with a fabricated kirigami-inspired e-skin. Apart from e-skin for prosthetics and robotics, the presented research will also be useful for obtaining high performance flexible circuits needed in many futuristic flexible electronics applications such as smart surgical tools, biosensors, implantable electronics/electroceuticals and flexible mobile phones