High Performance Local Oscillator Design for Next Generation Wireless Communication

Local Oscillator (LO) is an essential building block in modern wireless radios. In modern wireless radios, LO often serves as a reference of the carrier signal to modulate or demod- ulate the outgoing or incoming data. The LO signal should be a clean and stable source, such that the frequency or timing information of the carrier reference can be well-defined. However, as radio architecture evolves, the importance of LO path design has become much more important than before. Of late, many radio architecture innovations have exploited sophisticated LO generation schemes to meet the ever-increasing demands of wireless radio performances. The focus of this thesis is to address challenges in the LO path design for next-generation high performance wireless radios. These challenges include (1) Congested spectrum at low radio frequency (RF) below 5GHz (2) Continuing miniaturization of integrated wireless radio, and (3) Fiber-fast (>10Gb/s) mm-wave wireless communication. The thesis begins with a brief introduction of the aforementioned challenges followed by a discussion of the opportunities projected to overcome these challenges. To address the challenge of congested spectrum at frequency below 5GHz, novel ra- dio architectures such as cognitive radio, software-defined radio, and full-duplex radio have drawn significant research interest. Cognitive radio is a radio architecture that opportunisti- cally utilize the unused spectrum in an environment to maximize spectrum usage efficiency. Energy-efficient spectrum sensing is the key to implementing cognitive radio. To enable energy-efficient spectrum sensing, a fast-hopping frequency synthesizer is an essential build- ing block to swiftly sweep the carrier frequency of the radio across the available spectrum. Chapter 2 of this thesis further highlights the challenges and trade-offs of the current LO gen- eration scheme for possible use in sweeping LO-based spectrum analysis. It follows by intro- duction of the proposed fast-hopping LO architecture, its implementation and measurement results of the validated prototype. Chapter 3 proposes an embedded phase-shifting LO-path design for wideband RF self-interference cancellation for full-duplex radio. It demonstrates a synergistic design between the LO path and signal to perform self-interference cancellation. To address the challenge of continuing miniaturization of integrated wireless radio, ring oscillator-based frequency synthesizer is an attractive candidate due to its compactness. Chapter 4 discussed the difficulty associated with implementing a Phase-Locked Loop (PLL) with ultra-small form-factor. It further proposes the concept sub-sampling PLL with time- based loop filter to address these challenges. A 65nm CMOS prototype and its measurement result are presented for validation of the concept. In shifting from RF to mm-wave frequencies, the performance of wireless communication links is boosted by significant bandwidth and data-rate expansion. However, the demand for data-rate improvement is out-pacing the innovation of radio architectures. A >10Gb/s mm-wave wireless communication at 60GHz is required by emerging applications such as virtual-reality (VR) headsets, inter-rack data transmission at data center, and Ultra-High- Definition (UHD) TV home entertainment systems. Channel-bonding is considered to be a promising technique for achieving >10Gb/s wireless communication at 60GHz. Chapter 5 discusses the fundamental radio implementation challenges associated with channel-bonding for 60GHz wireless communication and the pros and cons of prior arts that attempted to address these challenges. It is followed by a discussion of the proposed 60GHz channel- bonding receiver, which utilizes only a single PLL and enables both contiguous and non- contiguous channel-bonding schemes. Finally, Chapter 6 presents the conclusion of this thesis

A 5-Gb/s 66 dB CMOS variable-gain amplifier with reconfigurable DC-offset cancellation for multi-standard applications

This paper proposes a variable gain amplifier (VGA) with reconfigurable DC-offset cancellation (DCOC) for multi-standard applications. In this design, a cell-based design method and some bandwidth extension technologies are adopted to achieve a high data rate and a wide gain control range simultaneously. In addition, the DCOC having a tunable lower-cutoff frequency can make an optimum compromise between BER and SNR according to the specified baseband standard. The measurements show that the VGA achieves a gain control range from −6 dB to 60 dB, a bandwidth beyond 3 GHz, and a tunable lower-cutoff frequency from 0 to 300 kHz. When entering a 2 23 −1 pseudo-random bit sequence signal at 5 Gb/s, the VGA consumes 17 mW from a 1.2-V supply and the output data peak-to-peak jitter is less than 40 ps. The VGA is fabricated in a 90-nm CMOS process with a chip size (including all pads) of 0.52×0.5 mm 2

A Novel Long-Range Passive UHF RFID System over Twisted-pair Cable

Radio Frequency Identification (RFID) is one of the most representative, rapidly growing, and highly extendable technologies, which uses electromagnetic waves in accordance with specific communications standards and regulations to identify, track, or even localise desired objects. However, due to its high cost, limited read range, and uncertain reliability, its adoption still lags, especially in large-scale organisations. Even though an RFID distributed antenna system (DAS) can greatly improve the detection range and read rate of a single reader when system uses different combinations of antenna states with frequency and phase hopping, the lossy and heavy coaxial cables between reader and antennas still limits the system coverage and design flexibility for wide-area passive UHF RFID applications. In order to develop a cost-efficient and flexibly-installed passive RFID DAS, a novel large-range passive UHF RFID system over twisted-pair cable is proposed in this dissertation. This new system consists of one baseband central controller and one antenna subsystem, connected by a commonly used twisted-pair cable. It is shown that transmitting/receiving low frequency baseband signals over a twisted-pair cable can significantly reduce cable attenuation and extend the communication distance. A simulation is conducted to demonstrate that frequency and phase hopping can also be remotely controlled to fit this system structure by slightly varying the frequency or phase of the input reference signal of the frequency synthesis system. The features of twisted-pair cable in terms of its low cost, light weight, and bend radius greatly improve the design and installation flexibility of an RFID system. The implemented system is designed based on the ISO 18000-6C and EPC Class 1 Generation 2 standards, and can operate according to FCC (902-928 MHz) and ETSI (865-868MHz) regulations. The results of the measurement show the reader can achieve a sensitivity of - 94.5 dBm over 30 m Cat5e cable, and its sensitivity can still remain at around -94.2 dBm over 150 m Cat5e cable. The experimental results of tag detection show that the passive tags can be successfully detected over a 6 m wireless range following a 300 m of twisted-pair cable between the central controller and antenna. This detection range cannot be achieved by existing commercial RFID systems. Since the transmission and reception in a RFID system are simultaneous, finite isolation of the circulator/directional coupler and environmentally dependent reflection ratio of the antenna lead to serious leakage problems. Leakage can directly cause sensitivity degradation due to saturation of the RF components. A fast leakage suppression block is developed in efforts to solve this problem. Measurements show that this new canceller can deliver an average suppression of 36.9 dB, and this excellent performance remains when the system uses frequency hopping. With help of an improved scanning algorithm, this canceller can find its optimal status within 38 ms, and this settling time is short enough for most commercial RFID readers. By reducing the number of voltage samples taken, the convergence time can be further improved. To fully investigate this new passive UHF RFID system value, a comparison study between the new system and a commercial system is conducted. This new automatic passive UHF RFID system is confirmed to deliver high performance long-range passive tag detection. Particular advantages are shown in the fast tag read rate and capability of uplink SNR improvement. This novel system is also superior to conventional RFID systems in terms of link distance, link cost, and installation flexibility

Investigations of an On-body Reflectometer Probe

Radar can be utilized to detect the mechanical heart activity and is a potential alternative to today’s heartbeat monitoring techniques in medicine. It can detect details of the heart activity, such as filling and ejection of heart chambers and opening and closing of heart valves. This is due to the radars ability to detect movements and direction of motion. Compared to electrocardiogram and ultrasound it has the advantage that it is a contactless measurement. The objective of this thesis is the development of a proof-of-concept prototype of a novel microwave on-body sensor for heartbeat detection, which can be used inside an MRI system and which could provide prospective triggering information. The main idea is to use a microwave sensor (reflectometer) with an on-body antenna illuminating the heart and detecting the reflected signal. The measurement is based on the evaluation of the heart-related time-dependent reflection coefficient of the antenna, by minimizing the static and respiration-related components of the reflection coefficient. In a first step, this is done by minimizing the antenna mismatch with an automatic impedance matching circuit after the placement of the antenna on the chest of an individual; the antenna mismatch is dependent on the position and the individual body properties. In a second step the residual static and slow variation signal from respiration is suppressed by a canceller circuit (well-known from CW radar technology as reflected power canceller). With the reflectometer sensor system consisting of a CW signal generator (transmitter, Tx), on-body antenna, adaptive impedance matching circuit and demodulator circuit as part of the reflected signal canceller, the performance of each component influences the performance of the sensor system. Thus, the thesis concentrates on the design of the circuits and the antenna but also investigates the wave propagation scenario of the sensor applied to a human chest. The signals measured with the microwave sensor are compared with a standard measurement method for heart activity, a heart sound measurement. This is used in order to assess the obtained signal and relate the signal states to certain heart states. The measured radar signals are found to be sensitive to position of the sensor, the individual and the posture of the individual, making the interpretation of the signals challenging

High-speed Time-interleaved Digital-to-Analog Converter (TI-DAC) for Self-Interference Cancellation Applications

Nowadays, the need for higher data-rate is constantly growing to enhance the quality of the daily communication services. The full-duplex (FD) communication is exemplary method doubling the data-rate compared to half-duplex one. However, part of the strong output signal of the transmitter interferes to the receiver-side because they share the same antenna with limited attenuation and, as a result, the receiver’s performance is corrupted. Hence, it is critical to remove the leakage signal from the receiver’s path by designing another block called self-interference cancellation (SIC). The main goal of this dissertation is to develop the SIC block embedded in the current-mode FD receivers. To this end, the regenerated cancellation current signal is fed to the inputs of the base-band filter and after the mixer of a (direct-conversion) current-mode FD receiver. Since the pattern of the transmitter (the digital signal generated by DSP) is known, a high-speed digital-to-Analog converter (DAC) with medium-resolution can perfectly suppress main part of the leakage on the receiver path. A capacitive DAC (CDAC) is chosen among the available solutions because it is compatible with advanced CMOS technology for high-speed application and the medium-resolution designs. Although the main application of the design is to perform the cancellation, it can also be employed as a stand-alone DAC in the Analog (I/Q) transmitter. The SIC circuitry includes a trans-impedance amplifier (TIA), two DACs, high-speed digital circuits, and built-in-self-test section (BIST). According to the available specification for full-duplex communication system, the resolution and working frequency of the CDAC are calculated (designed) equal to 10-bit (3 binary+ 2 binary + 5 thermometric) and 1GHz, respectively. In order to relax the design of the TIA (settling time of the DAC), the CDAC implements using 2-way time-interleaved (TI) manner (the effective SIC frequency equals 2GHz) without using any calibration technique. The CDAC is also developed with the split-capacitor technique to lower the negative effects of the conventional binary-weighted DAC. By adding one extra capacitor on the left-side of the split-capacitor, LSB-side, the value of the split-capacitor can be chosen as an integer value of the unit capacitor. As a result, it largely enhances the linearity of the CADC and cancellation performance. If the block works as a stand-alone DAC with non-TI mode, the digital input code representing a Sinus waveform with an amplitude 1dB less than full-scale and output frequency around 10.74MHz, chosen by coherent sampling rule, then the ENOB, SINAD, SFDR, and output signal are 9.4-bit, 58.2 dB, 68.4dBc, and -9dBV. The simulated value of the |DNL| (static linearity) is also less than 0.7. The similar simulation was done in the SIC mode while the capacitive-array woks in the TI mode and cancellation current is set to the full-scale. Hence, the amount of cancelling the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. equals 51.3dB, 15.1 dB, 24dBc, 66.4 dB. The designed SIC cannot work as a closed-loop design. The layout was optimally drawn in order to minimize non-linearity, the power-consumption of the decoders, and reduce the complexity of the DAC. By distributing the thermometric cells across the array and using symmetrical switching scheme, the DAC is less subjected to the linear and gradient effect of the oxide. Based on the post-layout simulation results, the deviation of the design after drawing the layout is studied. To compare the results of the schematic and post-layout designs, the exact conditions of simulation above (schematic simulations) are used. When the block works as a stand-alone CDAC, the ENOB, SINAD, SFDR are 8.5-bit, 52.6 dB, 61.3 dBc. The simulated value of the |DNL| (static linearity) is also limited to 1.3. Likewise, the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. are equal to 44dB, 11.7 dB, 19 dBc, 55.7 dB

Hybrid DDS-PLL based reconfigurable oscillators with high spectral purity for cognitive radio

Analytical, design and simulation studies on the performance optimization of reconfigurable architecture of a Hybrid DDS – PLL are presented in this thesis. The original contributions of this thesis are aimed towards the DDS, the dithering (spur suppression) scheme and the PLL. A new design of Taylor series-based DDS that reduces the dynamic power and number of multipliers is a significant contribution of this thesis. This thesis compares dynamic power and SFDR achieved in the design of varieties of DDS such as Quartic, Cubic, Linear and LHSC. This thesis proposes two novel schemes namely “Hartley Image Suppression” and “Adaptive Sinusoidal Interference Cancellation” overcoming the low noise floor of traditional dithering schemes. The simulation studies on a Taylor series-based DDS reveal an improvement in SFDR from 74 dB to 114 dB by using Least Mean Squares -Sinusoidal Interference Canceller (LM-SIC) with the noise floor maintained at -200 dB. Analytical formulations have been developed for a second order PLL to relate the phase noise to settling time and Phase Margin (PM) as well as to relate jitter variance and PM. New expressions relating phase noise to PM and lock time to PM are derived. This thesis derives the analytical relationship between the roots of the characteristic equation of a third order PLL and its performance metrics like PM, Gardner’s stability factor, jitter variance, spur gain and ratio of noise power to carrier power. This thesis presents an analysis to relate spur gain and capacitance ratio of a third order PLL. This thesis presents an analytical relationship between the lock time and the roots of its characteristic equation of a third order PLL. Through Vieta’s circle and Vieta’s angle, the performance metrics of a third order PLL are related to the real roots of its characteristic equation

Low complexity blind and data-aided IQ imbalance compensation methods for low-IF receivers

Low-IF and Zero-IF (direct conversion) down converters showed a great potential in implementing multi standard single chip solutions, eliminating the need to use off chip components and so reduce the area and the cost of the wireless receivers. One of the main performance limitations in the low-IF & Zero-IF down-converters is the components mismatch between the in-phase path and the quadrature-path named the IQ Imbalance (IQI) which limits the achievable image rejection ratio (IRR) of the down converters. Many techniques had been proposed to enhance the achievable IRR either by using calibration methods, e.g. using lab calibration, or by doing online compensation during signal reception. In this work those techniques are reviewed, proposing three new methods for blind IQI compensation techniques, the first proposed method targets the low input signal to interference ratio (low SIRin) while the second and third methods targets the moderate and high SIRin, showing that the proposed methods reach better performance and/or lower complexity than the methods already introduced in the literature. Also two techniques to perform data aided IQI compensation are introduced exploiting pilot symbols within the desired signal with no prior knowledge about the image signal. The first method exploits a preamble sequence assuming slow fading condition while the second approach exploits a sequence of pilots to compensate for the IQI being suitable for fast fading conditions as well. Simulation results showed that the proposed data aided techniques achieved shorter convergence time and higher image rejection ratio compared to the blind methods at high SNR values