A digital polar transmitter for multi-band OFDM Ultra-WideBand

Linear power amplifiers used to implement the Ultra-Wideband standard must be backed off from optimum power efficiency to meet the standard specifications and the power efficiency suffers. The problem of low efficiency can be mitigated by polar modulation. Digital polar architectures have been employed on numerous wireless standards like GSM, EDGE, and WLAN, where the fractional bandwidths achieved are only about 1%, and the power levels achieved are often in the vicinity of 20 dBm. Can the architecture be employed on wireless standards with low-power and high fractional bandwidth requirements and yet achieve good power efficiency? To answer these question, this thesis studies the application of a digital polar transmitter architecture with parallel amplifier stages for UWB. The concept of the digital transmitter is motivated and inspired by three factors. First, unrelenting advances in the CMOS technology in deep-submicron process and the prevalence of low-cost Digital Signal processing have resulted in the realization of higher level of integration using digitally intensive approaches. Furthermore, the architecture is an evolution of polar modulation, which is known for high power efficiency in other wireless applications. Finally, the architecture is operated as a digital-to-analog converter which circumvents the use of converters in conventional transmitters. Modeling and simulation of the system architecture is performed on the Agilent Advanced Design System Ptolemy simulation platform. First, by studying the envelope signal, we found that envelope clipping results in a reduction in the peak-to-average power ratio which in turn improves the error vector magnitude performance (figure of merit for the study). In addition, we have demonstrated that a resolution of three bits suffices for the digital polar transmitter when envelope clipping is performed. Next, this thesis covers a theoretical derivation for the estimate of the error vector magnitude based on the resolution, quantization and phase noise errors. An analysis on the process variations - which result in gain and delay mismatches - for a digital transmitter architecture with four bits ensues. The above studies allow RF designers to estimate the number of bits required and the amount of distortion that can be tolerated in the system. Next, a study on the circuit implementation was conducted. A DPA that comprises 7 parallel RF amplifiers driven by a constant RF phase-modulated signal and 7 cascode transistors (individually connected in series with the bottom amplifiers) digitally controlled by a 3-bit digitized envelope signal to reconstruct the UWB signal at the output. Through the use of NFET models from the IBM 130-nm technology, our simulation reveals that our DPA is able to achieve an EVM of - 22 dB. The DPA simulations have been performed at 3.432 GHz centre frequency with a channel bandwidth of 528 MHz, which translates to a fractional bandwidth of 15.4%. Drain efficiencies of 13.2/19.5/21.0% have been obtained while delivering -1.9/2.5/5.5 dBm of output power and consuming 5/9/17 mW of power. In addition, we performed a yield analysis on the digital polar amplifier, based on unit-weighted and binary-weighted architecture, when gain variations are introduced in all the individual stages. The dynamic element matching method is also introduced for the unit-weighted digital polar transmitter. Monte Carlo simulations reveal that when the gain of the amplifiers are allowed to vary at a mean of 1 with a standard deviation of 0.2, the binary-weighted architecture obtained a yield of 79%, while the yields of the unit-weighted architectures are in the neighbourhood of 95%. Moreover, the dynamic element matching technique demonstrates an improvement in the yield by approximately 3%. Finally, a hardware implementation for this architecture based on software-defined arbitrary waveform generators is studied. In this section, we demonstrate that the error vector magnitude results obtained with a four-stage binary-weighted digital polar transmitter under ideal combining conditions fulfill the European Computer Manufacturers Association requirements. The proposed experimental setup, believed to be the first ever attempted, confirm the feasibility of a digital polar transmitter architecture for Ultra-Wideband. In addition, we propose a number of power combining techniques suitable for the hardware implementation. Spatial power combining, in particular, shows a high potential for the digital polar transmitter architecture. The above studies demonstrate the feasibility of the digital polar architecture with good power efficiency for a wideband wireless standard with low-power and high fractional bandwidth requirements

Energy Efficient RF Transmitter Design using Enhanced Breakdown Voltage SOI-CMOS Compatible MESFETs

abstract: The high cut-off frequency of deep sub-micron CMOS technologies has enabled the integration of radio frequency (RF) transceivers with digital circuits. However, the challenging point is the integration of RF power amplifiers, mainly due to the low breakdown voltage of CMOS transistors. Silicon-on-insulator (SOI) metal semiconductor field effect transistors (MESFETs) have been introduced to remedy the limited headroom concern in CMOS technologies. The MESFETs presented in this thesis have been fabricated on different SOI-CMOS processes without making any change to the standard fabrication steps and offer 2-30 times higher breakdown voltage than the MOSFETs on the same process. This thesis explains the design steps of high efficiency and wideband RF transmitters using the proposed SOI-CMOS compatible MESFETs. This task involves DC and RF characterization of MESFET devices, along with providing a compact Spice model for simulation purposes. This thesis presents the design of several SOI-MESFET RF power amplifiers operating at 433, 900 and 1800 MHz with ~40% bandwidth. Measurement results show a peak power added efficiency (PAE) of 55% and a peak output power of 22.5 dBm. The RF-PAs were designed to operate in Class-AB mode to minimize the linearity degradation. Class-AB power amplifiers lead to poor power added efficiency, especially when fed with signals with high peak to average power ratio (PAPR) such as wideband code division multiple access (W-CDMA). Polar transmitters have been introduced to improve the efficiency of RF-PAs at backed-off powers. A MESFET based envelope tracking (ET) polar transmitter was designed and measured. A low drop-out voltage regulator (LDO) was used as the supply modulator of this polar transmitter. MESFETs are depletion mode devices; therefore, they can be configured in a source follower configuration to have better stability and higher bandwidth that MOSFET based LDOs. Measurement results show 350 MHz bandwidth while driving a 10 pF capacitive load. A novel polar transmitter is introduced in this thesis to alleviate some of the limitations associated with polar transmitters. The proposed architecture uses the backgate terminal of a partially depleted transistor on SOI process, which relaxes the bandwidth and efficiency requirements of the envelope amplifier in a polar transmitter. The measurement results of the proposed transmitter demonstrate more than three times PAE improvement at 6-dB backed-off output power, compared to the traditional RF transmitters.Dissertation/ThesisPh.D. Electrical Engineering 201

Radio-Communications Architectures

Wireless communications, i.e. radio-communications, are widely used for our different daily needs. Examples are numerous and standard names like BLUETOOTH, WiFI, WiMAX, UMTS, GSM and, more recently, LTE are well-known [Baudoin et al. 2007]. General applications in the RFID or UWB contexts are the subject of many papers. This chapter presents radio-frequency (RF) communication systems architecture for mobile, wireless local area networks (WLAN) and connectivity terminals. An important aspect of today's applications is the data rate increase, especially in connectivity standards like WiFI and WiMAX, because the user demands high Quality of Service (QoS). To increase the data rate we tend to use wideband or multi-standard architecture. The concept of software radio includes a self-reconfigurable radio link and is described here on its RF aspects. The term multi-radio is preferred. This chapter focuses on the transmitter, yet some considerations about the receiver are given. An important aspect of the architecture is that a transceiver is built with respect to the radio-communications signals. We classify them in section 2 by differentiating Continuous Wave (CW) and Impulse Radio (IR) systems. Section 3 is the technical background one has to consider for actual applications. Section 4 summarizes state-of-the-art high data rate architectures and the latest research in multi-radio systems. In section 5, IR architectures for Ultra Wide Band (UWB) systems complete this overview; we will also underline the coexistence and compatibility challenges between CW and IR systems

Integrated circuits for efficient power delivery using pulse-width-modulation

Circuits and architectures for efficient power delivery have become crucial in emerging smart systems. Switching power amplifiers (PA) are very attractive for such applications, because they exhibit better efficiency compared to linear PA designs, due to saturated operation. Switching PAs also allow for utilization of deep submicron CMOS technologies, due to which these designs can be easily integrated with digital circuits, and can benefit from process scaling, in performance as well as in area. Pulse-width-modulation (PWM) is commonly used with switching PAs. A PWM signal typically employs a high-frequency switching pulse waveform as a carrier signal, wherein the pulse-width or duty-cycle of each pulse is modulated by a given low-frequency input signal. The carrier frequency can vary from several kHz to GHz, and is typically determined by the target application. In this thesis, efficient power-delivery circuits that use PWM with switching class-D stages are presented. Advanced circuit techniques, as well as architectures for PWM are proposed to enhance efficiency and circumvent the limitations of conventional architectures. A digitally-intensive transmitter using RF-PWM with a class-D PA is described in the first part of the thesis. The use of carrier switching for alleviating the dynamic range limitation that can be observed in classical RF-PWM implementations is introduced. The approach employs the full carrier frequency for half of the amplitude range, and the second harmonic of half of the carrier frequency, for the remainder of the amplitude range. This concept not only allows the transmitter to drive modulated signals with large peak-to-average power ratio (PAPR), but also improves the back-off efficiency due to reduced switching losses in the half carrier-frequency mode. A glitch-free phase selector is proposed that removes the deleterious glitches that can occur at the input data transitions. The phase-selector also prevents D flip-flop setup-and-hold time violations. The transmitter has been implemented in a 130-nm CMOS process. The measured peak output power and power-added-efficiency (PAE) are 25.6 dBm and 34%, respectively. While driving 802.11g 20-MHz 64-QAM OFDM signals, the average measured output power is 18.3 dBm and the PAE is 16%, with an EVM of -25.5 dB. The second part of the thesis describes a high-speed driver that provides a PWM output using a class-D PA. A PLL-based architecture is employed which eliminates the requirement for a precise ramp or triangular signal generator, and a high-speed comparator, which are typically used for PWM generation. Multi-level signaling is proposed to enhance back-off as well as peak efficiency, which is critical for signals with high PAPR. A differential, folded PWM scheme is introduced to achieve highly linear operation. 3-level operation is achieved without the requirement for additional supply source or sink paths, while 5-level operation is achieved with additional supply source and sink paths, compared to 2-level operation. The PWM driver has been implemented in a 130-nm CMOS process and can operate with a switching frequency of 40-to-170 MHz. For 2/3/5-level PA operation, with a 500 kHz sinusoidal input and 60 MHz switching frequency, the measured THD is -61/-62/-53 dB and corresponding efficiency is 71/83/86% with 175/200/220 mW output power level, respectively. Performance has also been verified for 2/3-level PA operation with a high PAPR signal with 500 kHz bandwidth. While intended as a general purpose amplifier, the approach is well-suited for applications such as power-line communications (PLC). The final part of the thesis introduces an efficient buck/buck-boost reconfigurable LED driver that supports PWM and PFM operation. The driver is based on peak current control. Rectified sin as well as sin² functions are employed in the reference signal to improve the power factor (PF) and total harmonic distortion (THD) of the buck and buck-boost converters. The design ensures that the peak of the inductor current maintains a constant level that is invariant for different AC line voltages. The operating mode of the design can be changed between PWM and PFM. The LED driver has been implemented in a 130-nm CMOS process. PF and THD are improved when the proposed reference is employed, and peak PF and lowest THD are 0.995/0.983/0.996 and 7.8/6.2/3.5% for the buck (PWM), buck (PFM), buck-boost (PFM) cases, respectively. The corresponding peak efficiency for the three cases is 88/92/91%, respectively.Electrical and Computer Engineerin

Digital Radio Encoding and Power Amplifier Design for Multimode and Multiband Wireless Communications

The evolution of wireless technology has necessitated the support of multiple communication standards by mobile devices. At present, multiple chipsets/radios operating at predefined sets of modulation schemes, frequency bands, bandwidths and output power levels are used to achieve this objective. This leads to higher component counts, increased cost and limits the capacity to cope with future communication standards. In order to tackle different wireless standards using a single chipset, digital circuits have been increasingly deployed in radios and demonstrated re-configurability in different modulation schemes (multimode) and frequency bands (multiband). Despite efforts and progress made in digitizing the entire radio, the power amplifier (PA) is still designed using an conventional approach and has become the bottleneck in digital transmitters, in terms of low average power efficiency, poor compatibility with modern CMOS technology and limited re-configurability. This research addresses these issues from two aspects. The first half of the thesis investigates signal encoding issues between the modulator and PA. We propose, analyze and evaluate a new hybrid amplitude/time signal encoding scheme that significantly improves the coding efficiency and dynamic range of a digitally modulated power amplifier (DMPA) without significantly increasing design complexity. The proposed hybrid amplitude/time encoding scheme combines both the amplitude domain and the time domain to optimally encode information. Experimental results show that hybrid amplitude/time encoding results in a 35% increase in the average coding efficiency with respect to conventional time encoding, and is only 6.7% lower than peak efficiency when applied to a Wireless Local Area Network (WLAN) signal with a peak to average power ratio equal to 9.9 dB. A new DMPA architecture, based on the proposed hybrid encoding, is also proposed. The second half of this thesis presents the design, analysis and implementation of a CMOS PA that is amenable to the proposed hybrid encoding scheme. A multi-way current mode class-D PA architecture has been proposed and realized in 130 nm CMOS technology. The designed PA has satisfied the objectives of wide bandwidth (1.5 GHz - 2.7 GHz at 1 dB output power), and high efficiency (PAE 63%) in addition to demonstrating linear responses using the proposed digital encoding. A complete digital transmitter combining the encoder and the multi-way PA was also investigated. The overall efficiency is 27% modulating 7.3 dB peak to average power ratio QAM signals

Analog dithering techniques for highly linear and efficient transmitters

The current thesis is about investigation of new methods and techniques to be able to utilize the switched mode amplifiers, for linear and efficient applications. Switched mode amplifiers benefit from low overlap between the current and voltage wave forms in their output terminals, but they seriously suffer from nonlinearity. This makes it impossible to use them to amplify non-constant envelope message signals, where very high linearity is expected. In order to do that, dithering techniques are studied and a full linearity analysis approach is developed, by which the linearity performance of the dithered amplifier can be analyzed, based on the dithering level and frequency. The approach was based on orthogonalization of the equivalent nonlinearity and is capable of prediction of both co-channel and adjacent channel nonlinearity metrics, for a Gaussian complex or real input random signal. Behavioral switched mode amplifier models are studied and new models are developed, which can be utilized to predict the nonlinear performance of the dithered power amplifier, including the nonlinear capacitors effects. For HFD application, self-oscillating and asynchronous sigma delta techniques are currently used, as pulse with modulators (PWM), to encode a generic RF message signal, on the duty cycle of an output pulse train. The proposed models and analysis techniques were applied to this architecture in the first phase, and the method was validated with measurement on a prototype sample, realized in 65 nm TSMC CMOS technology. Afterwards, based on the same dithering phenomenon, a new linearization technique was proposed, which linearizes the switched mode class D amplifier, and at the same time can reduce the reactive power loss of the amplifier. This method is based on the dithering of the switched mode amplifier with frequencies lower than the band-pass message signal and is called low frequency dithering (LFD). To test this new technique, two test circuits were realized and the idea was applied to them. Both of the circuits were of the hard nonlinear type (class D) and are integrated CMOS and discrete LDMOS technologies respectively. The idea was successfully tested on both test circuits and all of the linearity metric predictions for a digitally modulated RF signal and a random signal were compared to the measurements. Moreover a search method to find the optimum dither frequency was proposed and validated. Finally, inspired by averaging interpretation of the dithering phenomenon, three new topologies were proposed, which are namely DLM, RF-ADC and area modulation power combining, which are all nonlinear systems linearized with dithering techniques. A new averaging method was developed and used for analysis of a Gilbert cell mixer topology, which resulted in a closed form relationship for the conversion gain, for long channel devices