1,292 research outputs found
A Bang-Bang All-Digital PLL for Frequency Synthesis
abstract: Phase locked loops are an integral part of any electronic system that requires a clock signal and find use in a broad range of applications such as clock and data recovery circuits for high speed serial I/O and frequency synthesizers for RF transceivers and ADCs. Traditionally, PLLs have been primarily analog in nature and since the development of the charge pump PLL, they have almost exclusively been analog. Recently, however, much research has been focused on ADPLLs because of their scalability, flexibility and higher noise immunity. This research investigates some of the latest all-digital PLL architectures and discusses the qualities and tradeoffs of each. A highly flexible and scalable all-digital PLL based frequency synthesizer is implemented in 180 nm CMOS process. This implementation makes use of a binary phase detector, also commonly called a bang-bang phase detector, which has potential of use in high-speed, sub-micron processes due to the simplicity of the phase detector which can be implemented with a simple D flip flop. Due to the nonlinearity introduced by the phase detector, there are certain performance limitations. This architecture incorporates a separate frequency control loop which can alleviate some of these limitations, such as lock range and acquisition time.Dissertation/ThesisM.S. Electrical Engineering 201
Recommended from our members
Architectures and Circuits Leveraging Injection-Locked Oscillators for Ultra-Low Voltage Clock Synthesis and Reference-less Receivers for Dense Chip-to-Chip Communications
High performance computing is critical for the needs of scientific discovery and economic competitiveness. An extreme-scale computing system at 1000x the performance of todayโs petaflop machines will exhibit massive parallelism on multiple vertical fronts, from thousands of computational units on a single processor to thousands of processors in a single data center. To facilitate such a massively-parallel extreme-scale computing, a key challenge is power. The challenge is not power associated with base computation but rather the problem of transporting data from one chip to another at high enough rates. This thesis presents architectures and techniques to achieve low power and area footprint while achieving high data rates in a dense very-short reach (VSR) chip-to-chip (C2C) communication network. High-speed serial communication operating at ultra-low supplies improves the energy-efficiency and lowers the power envelop of a system doing an exaflop of loops. One focus area of this thesis is clock synthesis for such energy-efficient interconnect applications operating at high speeds and ultra-low supplies. A sub-integer clockfrequency synthesizer is presented that incorporates a multi-phase injection-locked ring-oscillator-based prescaler for operation at an ultra-low supply voltage of 0.5V, phase-switching based programmable division for sub-integer clock-frequency synthesis, and automatic calibration to ensure injection lock. A record speed of 9GHz has been demonstrated at 0.5V in 45nm SOI CMOS. It consumes 3.5mW of power at 9.12GHz and 0.052 of area, while showing an output phase noise of -100dBc/Hz at 1MHz offset and RMS jitter of 325fs; it achieves a net of -186.5 in a 45-nm SOI CMOS process. This thesis also describes a receiver with a reference-less clocking architecture for high-density VSR-C2C links. This architecture simplifies clock-tree planning in dense extreme-scaling computing environments and has high-bandwidth CDR to enable SSC for suppressing EMI and to mitigate TX jitter requirements. It features clock-less DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The RX is implemented in 14nm CMOS and characterized at 19Gb/s. It is 1.5x faster that previous reference-less embedded-oscillator based designs with greater than 100MHz jitter tolerance bandwidth and recovers error-free data over VSR-C2C channels. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER 200MHz and the INL of the ILO-based phase-rotator (32- Steps/UI) is <1-LSB. Lastly, this thesis develops a time-domain delay-based modeling of injection locking to describe injection-locking phenomena in nonharmonic oscillators. The model is used to predict the locking bandwidth, and the locking dynamics of the locked oscillator. The model predictions are verified against simulations and measurements of a four-stage differential ring oscillator. The model is further used to predict the injection-locking behavior of a single-ended CMOS inverter based ring oscillator, the lock range of a multi-phase injection-locked ring-oscillator-based prescaler, as well as the dynamics of tracking injection phase perturbations in injection-locked masterslave oscillators; demonstrating its versatility in application to any nonharmonic oscillator
Strontium optical lattice clocks for practical realization of the metre and secondary representation of the second
We present a system of two independent strontium optical lattice standards
probed with a single shared ultra-narrow laser. The absolute frequency of the
clocks can be verified by the use of Er:fiber optical frequency comb with the
GPS-disciplined Rb frequency standard. We report hertz-level spectroscopy of
the clock line and measurements of frequency stability of the two strontium
optical lattice clocks.Comment: This is an author-created, un-copyedited version of an article
accepted for publication in Meas. Sci. Technol. The publisher is not
responsible for any errors or omissions in this version of the manuscript or
any version derived from it. The Version of Record is available online at
doi:10.1088/0957-0233/26/7/07520
A phase-locked frequency divide-by-3 optical parametric oscillator
Accurate phase-locked 3:1 division of an optical frequency was achieved, by
using a continuous-wave (cw) doubly resonant optical parametric oscillator. A
fractional frequency stability of 2*10^(-17) of the division process has been
achieved for 100s integration time. The technique developed in this work can be
generalized to the accurate phase and frequency control of any cw optical
parametric oscillator.Comment: 4 pages, 5 figures in a postscript file. To appear in a special issue
of IEEE Trans. Instr. & Meas., paper FRIA-2 presented at CPEM'2000
conference, Sydney, May 200
Recommended from our members
Noise shaping Asynchronous SAR ADC based time to digital converter
Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin
Low-to-Medium Power Single Chip Digital Controlled DC-DC Regulator for Point-of-Load Applications
A DC-DC converter for generating a DC output voltage includes: a digitally controlled pulse width modulator (DPWM) for controlling a switching power stage to supply a varying voltage to an inductor; and a digital voltage feedback circuit for controlling the DPWM in accordance with a feedback voltage corresponding to the DC output voltage, the digital voltage feedback circuit including: a first voltage controlled oscillator for converting the feedback voltage into a first frequency signal and to supply the first frequency signal to a first frequency discriminator; a second voltage controlled oscillator for converting a reference voltage into a second frequency signal and to supply the second frequency signal to a second frequency discriminator; a digital comparator for comparing digital outputs of the first and second frequency discriminators and for outputting a digital feedback signal; and a controller for controlling the DPWM in accordance with the digital feedback signal
๊ณ ์ ์๋ฆฌ์ผ ๋งํฌ๋ฅผ ์ํ ๊ณ ๋ฆฌ ๋ฐ์ง๊ธฐ๋ฅผ ๊ธฐ๋ฐ์ผ๋ก ํ๋ ์ฃผํ์ ํฉ์ฑ๊ธฐ
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2022. 8. ์ ๋๊ท .In this dissertation, major concerns in the clocking of modern serial links are discussed. As sub-rate, multi-standard architectures are becoming predominant, the conventional clocking methodology seems to necessitate innovation in terms of low-cost implementation. Frequency synthesis with active, inductor-less oscillators replacing LC counterparts are reviewed, and solutions for two major drawbacks are proposed. Each solution is verified by prototype chip design, giving a possibility that the inductor-less oscillator may become a proper candidate for future high-speed serial links.
To mitigate the high flicker noise of a high-frequency ring oscillator (RO), a reference multiplication technique that effectively extends the bandwidth of the following all-digital phase-locked loop (ADPLL) is proposed. The technique avoids any jitter accumulation, generating a clean mid-frequency clock, overall achieving high jitter performance in conjunction with the ADPLL. Timing constraint for the proper reference multiplication is first analyzed to determine the calibration points that may correct the existent phase errors. The weight for each calibration point is updated by the proposed a priori probability-based least-mean-square (LMS) algorithm. To minimize the time required for the calibration, each gain for the weight update is adaptively varied by deducing a posteriori which error source dominates the others. The prototype chip is fabricated in a 40-nm CMOS technology, and its measurement results verify the low-jitter, high-frequency clock generation with fast calibration settling. The presented work achieves an rms jitter of 177/223 fs at 8/16-GHz output, consuming 12.1/17-mW power.
As the second embodiment, an RO-based ADPLL with an analog technique that addresses the high supply sensitivity of the RO is presented. Unlike prior arts, the circuit for the proposed technique does not extort the RO voltage headroom, allowing high-frequency oscillation. Further, the performance given from the technique is robust over process, voltage, and temperature (PVT) variations, avoiding the use of additional calibration hardware. Lastly, a comprehensive analysis of phase noise contribution is conducted for the overall ADPLL, followed by circuit optimizations, to retain the low-jitter output. Implemented in a 40-nm CMOS technology, the frequency synthesizer achieves an rms jitter of 289 fs at 8 GHz output without any injected supply noise. Under a 20-mVrms white supply noise, the ADPLL suppresses supply-noise-induced jitter by -23.8 dB.๋ณธ ๋
ผ๋ฌธ์ ํ๋ ์๋ฆฌ์ผ ๋งํฌ์ ํด๋ฝํน์ ๊ด์ฌ๋๋ ์ฃผ์ํ ๋ฌธ์ ๋ค์ ๋ํ์ฌ ๊ธฐ์ ํ๋ค. ์ค์๋, ๋ค์ค ํ์ค ๊ตฌ์กฐ๋ค์ด ์ฑํ๋๊ณ ์๋ ์ถ์ธ์ ๋ฐ๋ผ, ๊ธฐ์กด์ ํด๋ผํน ๋ฐฉ๋ฒ์ ๋ฎ์ ๋น์ฉ์ ๊ตฌํ์ ๊ด์ ์์ ์๋ก์ด ํ์ ์ ํ์๋ก ํ๋ค. LC ๊ณต์ง๊ธฐ๋ฅผ ๋์ ํ์ฌ ๋ฅ๋ ์์ ๋ฐ์ง๊ธฐ๋ฅผ ์ฌ์ฉํ ์ฃผํ์ ํฉ์ฑ์ ๋ํ์ฌ ์์๋ณด๊ณ , ์ด์ ๋ฐ์ํ๋ ๋๊ฐ์ง ์ฃผ์ ๋ฌธ์ ์ ๊ณผ ๊ฐ๊ฐ์ ๋ํ ํด๊ฒฐ ๋ฐฉ์์ ํ์ํ๋ค. ๊ฐ ์ ์ ๋ฐฉ๋ฒ์ ํ๋กํ ํ์
์นฉ์ ํตํด ๊ทธ ํจ์ฉ์ฑ์ ๊ฒ์ฆํ๊ณ , ์ด์ด์ ๋ฅ๋ ์์ ๋ฐ์ง๊ธฐ๊ฐ ๋ฏธ๋์ ๊ณ ์ ์๋ฆฌ์ผ ๋งํฌ์ ํด๋ฝํน์ ์ฌ์ฉ๋ ๊ฐ๋ฅ์ฑ์ ๋ํด ๊ฒํ ํ๋ค.
์ฒซ๋ฒ์งธ ์์ฐ์ผ๋ก์จ, ๊ณ ์ฃผํ ๊ณ ๋ฆฌ ๋ฐ์ง๊ธฐ์ ๋์ ํ๋ฆฌ์ปค ์ก์์ ์ํ์ํค๊ธฐ ์ํด ๊ธฐ์ค ์ ํธ๋ฅผ ๋ฐฐ์ํํ์ฌ ๋ท๋จ์ ์์ ๊ณ ์ ๋ฃจํ์ ๋์ญํญ์ ํจ๊ณผ์ ์ผ๋ก ๊ทน๋ํ ์ํค๋ ํ๋ก ๊ธฐ์ ์ ์ ์ํ๋ค. ๋ณธ ๊ธฐ์ ์ ์งํฐ๋ฅผ ๋์ ์ํค์ง ์์ผ๋ฉฐ ๋ฐ๋ผ์ ๊นจ๋ํ ์ค๊ฐ ์ฃผํ์ ํด๋ฝ์ ์์ฑ์์ผ ์์ ๊ณ ์ ๋ฃจํ์ ํจ๊ป ๋์ ์ฑ๋ฅ์ ๊ณ ์ฃผํ ํด๋ฝ์ ํฉ์ฑํ๋ค. ๊ธฐ์ค ์ ํธ๋ฅผ ์ฑ๊ณต์ ์ผ๋ก ๋ฐฐ์ํํ๊ธฐ ์ํ ํ์ด๋ฐ ์กฐ๊ฑด๋ค์ ๋จผ์ ๋ถ์ํ์ฌ ํ์ด๋ฐ ์ค๋ฅ๋ฅผ ์ ๊ฑฐํ๊ธฐ ์ํ ๋ฐฉ๋ฒ๋ก ์ ํ์
ํ๋ค. ๊ฐ ๊ต์ ์ค๋์ ์ฐ์ญ์ ํ๋ฅ ์ ๊ธฐ๋ฐ์ผ๋กํ LMS ์๊ณ ๋ฆฌ์ฆ์ ํตํด ๊ฐฑ์ ๋๋๋ก ์ค๊ณ๋๋ค. ๊ต์ ์ ํ์ํ ์๊ฐ์ ์ต์ํ ํ๊ธฐ ์ํ์ฌ, ๊ฐ ๊ต์ ์ด๋์ ํ์ด๋ฐ ์ค๋ฅ ๊ทผ์๋ค์ ํฌ๊ธฐ๋ฅผ ๊ท๋ฉ์ ์ผ๋ก ์ถ๋ก ํ ๊ฐ์ ๋ฐํ์ผ๋ก ์ง์์ ์ผ๋ก ์ ์ด๋๋ค. 40-nm CMOS ๊ณต์ ์ผ๋ก ๊ตฌํ๋ ํ๋กํ ํ์
์นฉ์ ์ธก์ ์ ํตํด ์ ์์, ๊ณ ์ฃผํ ํด๋ฝ์ ๋น ๋ฅธ ๊ต์ ์๊ฐ์์ ํฉ์ฑํด ๋์ ํ์ธํ์๋ค. ์ด๋ 177/223 fs์ rms ์งํฐ๋ฅผ ๊ฐ์ง๋ 8/16 GHz์ ํด๋ฝ์ ์ถ๋ ฅํ๋ค.
๋๋ฒ์งธ ์์ฐ์ผ๋ก์จ, ๊ณ ๋ฆฌ ๋ฐ์ง๊ธฐ์ ๋์ ์ ์ ๋
ธ์ด์ฆ ์์กด์ฑ์ ์ํ์ํค๋ ๊ธฐ์ ์ด ํฌํจ๋ ์ฃผํ์ ํฉ์ฑ๊ธฐ๊ฐ ์ค๊ณ๋์๋ค. ์ด๋ ๊ณ ๋ฆฌ ๋ฐ์ง๊ธฐ์ ์ ์ ํค๋๋ฃธ์ ๋ณด์กดํจ์ผ๋ก์ ๊ณ ์ฃผํ ๋ฐ์ง์ ๊ฐ๋ฅํ๊ฒ ํ๋ค. ๋์๊ฐ, ์ ์ ๋
ธ์ด์ฆ ๊ฐ์ ์ฑ๋ฅ์ ๊ณต์ , ์ ์, ์จ๋ ๋ณ๋์ ๋ํ์ฌ ๋ฏผ๊ฐํ์ง ์์ผ๋ฉฐ, ๋ฐ๋ผ์ ์ถ๊ฐ์ ์ธ ๊ต์ ํ๋ก๋ฅผ ํ์๋ก ํ์ง ์๋๋ค. ๋ง์ง๋ง์ผ๋ก, ์์ ๋
ธ์ด์ฆ์ ๋ํ ํฌ๊ด์ ๋ถ์๊ณผ ํ๋ก ์ต์ ํ๋ฅผ ํตํ์ฌ ์ฃผํ์ ํฉ์ฑ๊ธฐ์ ์ ์ก์ ์ถ๋ ฅ์ ๋ฐฉํดํ์ง ์๋ ๋ฐฉ๋ฒ์ ๊ณ ์ํ์๋ค. ํด๋น ํ๋กํ ํ์
์นฉ์ 40-nm CMOS ๊ณต์ ์ผ๋ก ๊ตฌํ๋์์ผ๋ฉฐ, ์ ์ ๋
ธ์ด์ฆ๊ฐ ์ธ๊ฐ๋์ง ์์ ์ํ์์ 289 fs์ rms ์งํฐ๋ฅผ ๊ฐ์ง๋ 8 GHz์ ํด๋ฝ์ ์ถ๋ ฅํ๋ค. ๋ํ, 20 mVrms์ ์ ์ ๋
ธ์ด์ฆ๊ฐ ์ธ๊ฐ๋์์ ๋์ ์ ๋๋๋ ์งํฐ์ ์์ -23.8 dB ๋งํผ ์ค์ด๋ ๊ฒ์ ํ์ธํ์๋ค.1 Introduction 1
1.1 Motivation 3
1.1.1 Clocking in High-Speed Serial Links 4
1.1.2 Multi-Phase, High-Frequency Clock Conversion 8
1.2 Dissertation Objectives 10
2 RO-Based High-Frequency Synthesis 12
2.1 Phase-Locked Loop Fundamentals 12
2.2 Toward All-Digital Regime 15
2.3 RO Design Challenges 21
2.3.1 Oscillator Phase Noise 21
2.3.2 Challenge 1: High Flicker Noise 23
2.3.3 Challenge 2: High Supply Noise Sensitivity 26
3 Filtering RO Noise 28
3.1 Introduction 28
3.2 Proposed Reference Octupler 34
3.2.1 Delay Constraint 34
3.2.2 Phase Error Calibration 38
3.2.3 Circuit Implementation 51
3.3 IL-ADPLL Implementation 55
3.4 Measurement Results 59
3.5 Summary 63
4 RO Supply Noise Compensation 69
4.1 Introduction 69
4.2 Proposed Analog Closed Loop for Supply Noise Compensation 72
4.2.1 Circuit Implementation 73
4.2.2 Frequency-Domain Analysis 76
4.2.3 Circuit Optimization 81
4.3 ADPLL Implementation 87
4.4 Measurement Results 90
4.5 Summary 98
5 Conclusions 99
A Notes on the 8REF 102
B Notes on the ACSC 105๋ฐ
Millimeter-Scale and Energy-Efficient RF Wireless System
This dissertation focuses on energy-efficient RF wireless system with millimeter-scale dimension, expanding the potential use cases of millimeter-scale computing devices. It is challenging to develop RF wireless system in such constrained space. First, millimeter-sized antennae are electrically-small, resulting in low antenna efficiency. Second, their energy source is very limited due to the small battery and/or energy harvester. Third, it is required to eliminate most or all off-chip devices to further reduce system dimension. In this dissertation, these challenges are explored and analyzed, and new methods are proposed to solve them. Three prototype RF systems were implemented for demonstration and verification. The first prototype is a 10 cubic-mm inductive-coupled radio system that can be implanted through a syringe, aimed at healthcare applications with constrained space. The second prototype is a 3x3x3 mm far-field 915MHz radio system with 20-meter NLOS range in indoor environment. The third prototype is a low-power BLE transmitter using 3.5x3.5 mm planar loop antenna, enabling millimeter-scale sensors to connect with ubiquitous IoT BLE-compliant devices. The work presented in this dissertation improves use cases of millimeter-scale computers by presenting new methods for improving energy efficiency of wireless radio system with extremely small dimensions. The impact is significant in the age of IoT when everything will be connected in daily life.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147686/1/yaoshi_1.pd
Towards Very Large Scale Analog (VLSA): Synthesizable Frequency Generation Circuits.
Driven by advancement in integrated circuit design and fabrication technologies, electronic systems have become ubiquitous. This has been enabled powerful digital design tools that continue to shrink the design cost, time-to-market, and the size of digital circuits. Similarly, the manufacturing cost has been constantly declining for the last four decades due to CMOS scaling. However, analog systems have struggled to keep up with the unprecedented scaling of digital circuits. Even today, the majority of the analog circuit blocks are custom designed, do not scale well, and require long design cycles.
This thesis analyzes the factors responsible for the slow scaling of analog blocks, and presents a new design methodology that bridges the gap between traditional custom analog design and the modern digital design. The proposed methodology is utilized in implementation of the frequency generation circuits โ traditionally considered analog systems. Prototypes covering two different applications were implemented. The first synthesized all-digital phase-locked loop was designed for 400-460 MHz MedRadio applications and was fabricated in a 65 nm CMOS process. The second prototype is an ultra-low power, near-threshold 187-500 kHz clock generator for energy harvesting/autonomous applications. Finally, a digitally-controlled oscillator frequency resolution enhancement technique is presented which allows reduction of quantization noise in ADPLLs without introducing spurs.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/109027/1/mufaisal_1.pd
- โฆ