Design of 8-Bit CMOS Digital to Analog Converter

Digital to analog converter (DAC) is the main link between the digital and analog signal in the world of signal processing. High-speed DAC has been used widely as the data converter in video, radar and communication application. This project presents a high-speed current switching CMOS digital analog converter (DAC) that achieves 8-bit resolution with good differential non-linearity (DNL). The use of current switching creates a potential for speed improvement because current can be switch in and out of a circuit faster than the voltage. This converter is based on current division by using segmentation technique. In this approach, low DNL and glitch energy can be achieved by segmenting the two or three most significant bits of the DAC with an array of equal current sources rather than a binary array of current sources. This proposed segmented DAC employs two internal DACs that have its own advantages. The first internal DAC is used for the upper 3-bits MSBs. It is implemented by using equal current sources 0.25mA, with the incoming 3-bits MSBs converted to 7 control lines by the thermometer decoder, which will enable the 7-switched current cells. Thermometer decoder ensures good differential linearity for the DAC. The remaining 5 LSB bits of the converter will be controlled by the second internal DAC that use the R2R network to binary weight the O.25mA current source. The circuit of the DAC is designed by dividing into modules. The modules include thermometer decoder, latch, 5-bit LSB inverted R-2R ladder, 3-bit MSB current source, two-way CMOS current switch and the current to voltage converter. This circuit is simulated by using Tanner Tools Pro software, where the SCNA20um CMOS process with level-2 transistor parameters is used. The simulation results of the designed DAC shows a conversion rate of 7.2Mhz, a lNL of ±1.36 LSB, a DNL of ±D.05 LSB and a glitch energy of 30p V s with the power supply of ± 5V. The reduced differential nonlinearity (DNL) is achieved by utilizing the proposed technique

Design of 8-bit SAR-ADC CMOS

Successive approximation analog-to-digital converter (ADC) implemented in a conventional 0.18μm CMOS technology with low voltage. The SAR composite of sample-and-hold dummy switch compensation was employed, comparator is low-voltage latched and realized based on current-mode approach, control logic circuit and digital-to-analog conversion consists of binary weighted capacitor arrays for the differential inputs. The ADC has INL and DNL of 0.45 LSB for supply voltage 1.8V, at sampling rate 200 KS/S and signal to noise ratio distortion is 58.5 dB. This design is suitable for standard CMOS technology with low-power low-cost VLSI implementation. It is well applied when embedded into system-on-chip (SOC) circuit designs

Design of High Speed Comparator

A new CMOS dynamic comparator using dual input single output differential amplifier as latch stage suitable for high speed analog - to - digital converters with High Spee d, low power dissipation and immune to. Back - to - back inverter in the latch stage is replaced with dual - input single output differential amplifier. This topology completely removes the noise that is present in the input. The stru cture shows lower power dissipation and higher speed than the conventional comparators. The circuit is simulated with 1V DC supply voltage and 250 MHz clock frequency. The proposed topology is based on two cross coupled differential pairs positive feedback and switchable current source ces, has a lower power dissipation, higher speed, less area, and it is shown to be very robust against transistor mismatch, n oise immunity

Novel CCII-based Field Programmable Analog Array and its Application to a Sixth-Order Butterworth LPF

In this paper, a field programmable analog array (FPAA) is proposed. The proposed FPAA consists of seven configurable analog blocks (CABs) arranged in a hexagonal lattice such that the CABs are directly connected to each other. This structure improves the overall frequency response of the chip by decreasing the parasitic capacitances in the signal path. The CABS of the FPAA is based on a novel fully differential digitally programmable current conveyor (DPCCII). The programmability of the DPCCII is achieved using digitally controlled three-bit MOS ladder current division network. No extra biasing circuit is required to generate specific analog control voltage signals. The DPCCII has constant standby power consumption, offset voltage, bandwidth and harmonic distortions over all its programming range. A sixth-order Butterworth tunable LPF suitable for WLAN/WiMAX receivers is realized on the proposed FPAA. The filter power consumption is 5.4mW from 1V supply; it’s cutoff frequency is tuned from 5.2 MHz to 16.9 MHz. All the circuits are realized using 90nm CMOS technology from TSMC. All simulations are carried out using Cadence

Digital to analog conversion apparatus

A digital to analog converter which improves the accuracy of reconstruction of a sampled analog signal without requiring that the sampling rate of the original signal be increased to obtain such accuracy

CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current

Parametric Macromodels of Differential Drivers and Receivers

This paper addresses the modeling of differential drivers and receivers for the analog simulation of high-speed interconnection systems. The proposed models are based on mathematical expressions, whose parameters can be estimated from the transient responses of the modeled devices. The advantages of this macromodeling approach are: improved accuracy with respect to models based on simplified equivalent circuits of devices; improved numerical efficiency with respect to detailed transistor-level models of devices; hiding of the internal structure of devices; straightforward circuit interpretation; or implementations in analog mixed-signal simulators. The proposed methodology is demonstrated on example devices and is applied to the prediction of transient waveforms and eye diagrams of a typical low-voltage differential signaling (LVDS) data link

Differential temperature sensors: Review of applications in the test and characterization of circuits, usage and design methodology

Differential temperature sensors can be placed in integrated circuits to extract a signature ofthe power dissipated by the adjacent circuit blocks built in the same silicon die. This review paper firstdiscusses the singularity that differential temperature sensors provide with respect to other sensortopologies, with circuit monitoring being their main application. The paper focuses on the monitoringof radio-frequency analog circuits. The strategies to extract the power signature of the monitoredcircuit are reviewed, and a list of application examples in the domain of test and characterizationis provided. As a practical example, we elaborate the design methodology to conceive, step bystep, a differential temperature sensor to monitor the aging degradation in a class-A linear poweramplifier working in the 2.4 GHz Industrial Scientific Medical—ISM—band. It is discussed how,for this particular application, a sensor with a temperature resolution of 0.02 K and a high dynamicrange is required. A circuit solution for this objective is proposed, as well as recommendations for thedimensions and location of the devices that form the temperature sensor. The paper concludes with adescription of a simple procedure to monitor time variability.Postprint (published version

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin