366 research outputs found

    Design and evaluation of countermeasures against fault injection attacks and power side-channel leakage exploration for AES block cipher

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    Differential Fault Analysis (DFA) and Power Analysis (PA) attacks, have become the main methods for exploiting the vulnerabilities of physical implementations of block ciphers, currently used in a multitude of applications, such as the Advanced Encryption Standard (AES). In order to minimize these types of vulnerabilities, several mechanisms have been proposed to detect fault attacks. However, these mechanisms can have a signi cant cost, not fully covering the implementations against fault attacks or not taking into account the leakage of the information exploitable by the power analysis attacks. In this paper, four different approaches are proposed with the aim of protecting the AES block cipher against DFA. The proposed solutions are based on Hamming code and parity bits as signature generators for the internal state of the AES cipher. These allow to detect DFA exploitable faults, from bit to byte level. The proposed solutions have been applied to a T-box based AES block cipher implemented on Field Programmable Gate Array (FPGA). Experimental results suggest a fault coverage of 98.5% and 99.99% with an area penalty of 9% and 36% respectively, for the parity bit signature generators and a fault coverage of 100% with an area penalty of 18% and 42% respectively when Hamming code signature generator is used. In addition, none of the proposed countermeasures impose a frequency degradation, in respect to the unprotected cipher. The proposed work goes further in the evaluation of the proposed DFA countermeasures by evaluating the impact of these structures in terms of power side-channel. The obtained results suggest that no extra information leakage is produced that can be exploited by PA. Overall, the proposed DFA countermeasures provide a high fault coverage protection with a low cost in terms of area and power consumption and no PA security degradation

    Lightweight Cryptography Meets Threshold Implementation: A Case Study for SIMON

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    Securing data transmission has always been a challenge. While many cryptographic algorithms are available to solve the problem, many applications have tough area constraints while requiring high-level security. Lightweight cryptography aims at achieving high-level security with the benefit of being low cost. Since the late nineties and with the discovery of side channel attacks the approach towards cryptography has changed quite significantly. An attacker who can get close to a device can extract sensitive data by monitoring side channels such as power consumption, sound, or electromagnetic emanation. This means that embedded implementations of cryptographic schemes require protection against such attacks to achieve the desired level of security. In this work we combine a low-cost embedded cipher, Simon, with a stateof-the-art side channel countermeasure called Threshold Implementation (TI). We show that TI is a great match for lightweight cryptographic ciphers, especially for hardware implementation. Our implementation is the smallest TI of a block-cipher on an FPGA. This implementation utilizes 96 slices of a low-cost Spartan-3 FPGA and 55 slices a modern Kintex-7 FPGA. Moreover, we present a higher order TI which is resistant against second order attacks. This implementation utilizes 163 slices of a Spartan-3 FPGA and 95 slices of a Kintex-7 FPGA. We also present a state of the art leakage analysis and, by applying it to the designs, show that the implementations achieve the expected security. The implementations even feature a significant robustness to higher order attacks, where several million observations are needed to detect leakage

    Power Profile Obfuscation using RRAMs to Counter DPA Attacks

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    Side channel attacks, such as Differential Power Analysis (DPA), denote a special class of attacks in which sensitive key information is unveiled through information extracted from the physical device executing a cryptographic algorithm. This information leakage, known as side channel information, occurs from computations in a non-ideal system composed of electronic devices such as transistors. Power dissipation is one classic side channel source, which relays information of the data being processed. DPA uses statistical analysis to identify data-dependent correlations in sets of power measurements. Countermeasures against DPA focus on hiding or masking techniques at different levels of design abstraction and are typically associated with high power and area cost. Emerging technologies such as Resistive Random Access Memory (RRAM), offer unique opportunities to mitigate DPAs with their inherent memristor device characteristics such as variability in write time, ultra low power (0.1-3 pJ/bit), and high density (4F2). In this research, an RRAM based architecture is proposed to mitigate the DPA attacks by obfuscating the power profile. Specifically, a dual RRAM based memory module masks the power dissipation of the actual transaction by accessing both the data and its complement from the memory in tandem. DPA attack resiliency for a 128-bit AES cryptoprocessor using RRAM and CMOS memory modules is compared against baseline CMOS only technology. In the proposed AES architecture, four single port RRAM memory units store the intermediate state of the encryption. The correlation between the state data and sets of power measurement is masked due to power dissipated from inverse data access on dual RRAM memory. A customized simulation framework is developed to design the attack scenarios using Synopsys and Cadence tool suites, along with a Hamming weight DPA attack module. The attack mounted on a baseline CMOS architecture is successful and the full key is recovered. However, DPA attacks mounted on the dual CMOS and RRAM based AES cryptoprocessor yielded unsuccessful results with no keys recovered, demonstrating the resiliency of the proposed architecture against DPA attacks

    Differential Power Analysis of the SKINNY Family of Block Ciphers

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    The SKINNY family of lightweight block ciphers is well-researched in terms of standard cryptanalysis, but little has been done in the field of power analysis attacks. By sequentially dividing and conquering, univariate Differential Power Analysis attacks are performed against SKINNY. As the resulting diffusion from MixColumns introduces redundancy in terms of leakage, we introduce an alternative placement scheme for the tweak material in the related-tweakey setting to minimize leakage of the key material.Masteroppgave i informatikkINF399MAMN-INFMAMN-PRO

    Exploitation of Unintentional Information Leakage from Integrated Circuits

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    Unintentional electromagnetic emissions are used to recognize or verify the identity of a unique integrated circuit (IC) based on fabrication process-induced variations in a manner analogous to biometric human identification. The effectiveness of the technique is demonstrated through an extensive empirical study, with results presented indicating correct device identification success rates of greater than 99:5%, and average verification equal error rates (EERs) of less than 0:05% for 40 near-identical devices. The proposed approach is suitable for security applications involving commodity commercial ICs, with substantial cost and scalability advantages over existing approaches. A systematic leakage mapping methodology is also proposed to comprehensively assess the information leakage of arbitrary block cipher implementations, and to quantitatively bound an arbitrary implementation\u27s resistance to the general class of differential side channel analysis techniques. The framework is demonstrated using the well-known Hamming Weight and Hamming Distance leakage models, and approach\u27s effectiveness is demonstrated through the empirical assessment of two typical unprotected implementations of the Advanced Encryption Standard. The assessment results are empirically validated against correlation-based differential power and electromagnetic analysis attacks

    Methodologies for power analysis attacks on hardware implementations of AES

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    Side Channel Attacks (SCA) exploit weaknesses in implementations of cryptographic functions resulting from unintended inputs and outputs such as execution timing, power consumption, electromagnetic radiation, thermal and acoustic emanations. Power Analysis Attacks (PAA) are a type of SCA in which an attacker measures the power consumption of a cryptographic device during normal execution. An attempt is then made to uncover a relationship between the instantaneous power consumption and secret key information. PAAs can be subdivided into Simple Power Analysis (SPA), Differential Power Analysis (DPA), and Correlation Power Analysis (CPA). Many attacks have been documented since PAAs were first described in 1998. But since they often vary significantly, it is difficult to directly compare the vulnerability of the implementations used in each. Research is necessary to identify and develop standard methods of evaluating the vulnerability of cryptographic implementations to PAAs. This thesis defines methodologies for performing PAAs on hardware implementations of AES. The process is divided into identification, extraction, and evaluation stages. The extraction stage is outlined for both simulated power consumption waveforms as well as for waveforms captured from physical implementations. An AES encryption hardware design is developed for the experiment. The hardware design is synthesized with the Synopsys 130-nm CMOS standard cell library. Simulated instantaneous power consumption waveforms are generated with Synopsys PrimeTime PX. Single and multiple-bit DPA attacks are performed on the waveforms. Improvements are applied in order to automate and improve the precision and performance of the system. The attacks on the simulated power waveforms are successful. The correct key byte is identified in 15 of the 16 single-bit attacks after 10,000 traces. The single-bit attack which does not uniquely identify the correct key byte becomes successful after 15,000 or more traces are applied. The key byte is found in 36 of the 38 multiple-bit attacks. The main contribution of this work is a methodology and simulation environment which can be used to design hardware which is resistant to PAA and determine and compare vulnerability

    Side Channel Resistance Evaluation and Measurement

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    While unknown to most people, hardware implementation attacks provide a serious adversary for systems that contain sensitive data. Mission critical information can be extracted from a design with little effort from an attacker when they have access to the physical hardware. Thus designers try to mitigate this problem by using unique countermeasures styles. This work presents the first practical differential power analysis security evaluation of a countermeasure style called t-private logic. A PRESENT block cipher S-Box was implemented on a Virtex 5 FPGA as a reference platform. Both hardware and simulated power traces were collected. Statistical analyses were performed (CPA and Correlation enhanced collision attack) and our results revealed a first-order side channel attack vulnerability

    Enhancing Electromagnetic Side-Channel Analysis in an Operational Environment

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    Side-channel attacks exploit the unintentional emissions from cryptographic devices to determine the secret encryption key. This research identifies methods to make attacks demonstrated in an academic environment more operationally relevant. Algebraic cryptanalysis is used to reconcile redundant information extracted from side-channel attacks on the AES key schedule. A novel thresholding technique is used to select key byte guesses for a satisfiability solver resulting in a 97.5% success rate despite failing for 100% of attacks using standard methods. Two techniques are developed to compensate for differences in emissions from training and test devices dramatically improving the effectiveness of cross device template attacks. Mean and variance normalization improves same part number attack success rates from 65.1% to 100%, and increases the number of locations an attack can be performed by 226%. When normalization is combined with a novel technique to identify and filter signals in collected traces not related to the encryption operation, the number of traces required to perform a successful attack is reduced by 85.8% on average. Finally, software-defined radios are shown to be an effective low-cost method for collecting side-channel emissions in real-time, eliminating the need to modify or profile the target encryption device to gain precise timing information
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