From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

Transfer as a reciprocal process: How to foster receptivity to results of transdisciplinary research

Transdisciplinary research (TDR) seeks to address real-world problems and aims to be socially transformative. This normative objective extends beyond particular TDR projects, as real-world problems are embedded in concrete contexts but, at the same time, are also related to wider societal challenges that are not restricted to one context. Therefore, TDR generally entails transfer of knowledge and results to other contexts. However, the TDR discourse has mainly treated transfer efforts from the perspective of scientific generalization, translation and packaging of knowledge. Within this understanding of transfer, little attention has been paid to interplay between contexts and the role of new contexts themselves. This article is based on qualitative explorative research on four TDR projects. Its results were iteratively derived through project analysis, reflection on insights from the literature and discussions with TDR experts. We propose that transfer is a complex reciprocal process in which different types of knowledge are provided and transferred to other contexts, where knowledge is adapted, enriched and modified. In addition to project researchers, actors in other (pick-up) contexts also play an important role for successful transfer and appropriation of TDR results. Generating transfer potential within the duration of a project depends on being aware of potential pick-up contexts. To address the interdependent aspects of transfer (results, mediation, and appropriation in other contexts), we present a comprehensive model outlining TDR transfer processes. To support projects seeking to raise their transfer potential in a more conscious manner, we also formulate three overarching recommendations: 1) process results for transfer adequately, 2) identify and support intermediaries and, 3) increase awareness of and address other contexts. Considering these recommendations while also being aware of their interdependence may increase potential for transfer of knowledge and results to other contexts. Our conceptual understanding acknowledges the complexity and non-linearity of endeavors to take advantage of case-specifically gained knowledge and results in other contexts or at other scales

Efficient Neural Network Implementations on Parallel Embedded Platforms Applied to Real-Time Torque-Vectoring Optimization Using Predictions for Multi-Motor Electric Vehicles

The combination of machine learning and heterogeneous embedded platforms enables new potential for developing sophisticated control concepts which are applicable to the field of vehicle dynamics and ADAS. This interdisciplinary work provides enabler solutions -ultimately implementing fast predictions using neural networks (NNs) on field programmable gate arrays (FPGAs) and graphical processing units (GPUs)- while applying them to a challenging application: Torque Vectoring on a multi-electric-motor vehicle for enhanced vehicle dynamics. The foundation motivating this work is provided by discussing multiple domains of the technological context as well as the constraints related to the automotive field, which contrast with the attractiveness of exploiting the capabilities of new embedded platforms to apply advanced control algorithms for complex control problems. In this particular case we target enhanced vehicle dynamics on a multi-motor electric vehicle benefiting from the greater degrees of freedom and controllability offered by such powertrains. Considering the constraints of the application and the implications of the selected multivariable optimization challenge, we propose a NN to provide batch predictions for real-time optimization. This leads to the major contribution of this work: efficient NN implementations on two intrinsically parallel embedded platforms, a GPU and a FPGA, following an analysis of theoretical and practical implications of their different operating paradigms, in order to efficiently harness their computing potential while gaining insight into their peculiarities. The achieved results exceed the expectations and additionally provide a representative illustration of the strengths and weaknesses of each kind of platform. Consequently, having shown the applicability of the proposed solutions, this work contributes valuable enablers also for further developments following similar fundamental principles.Some of the results presented in this work are related to activities within the 3Ccar project, which has received funding from ECSEL Joint Undertaking under grant agreement No. 662192. This Joint Undertaking received support from the European Union’s Horizon 2020 research and innovation programme and Germany, Austria, Czech Republic, Romania, Belgium, United Kingdom, France, Netherlands, Latvia, Finland, Spain, Italy, Lithuania. This work was also partly supported by the project ENABLES3, which received funding from ECSEL Joint Undertaking under grant agreement No. 692455-2

Design and Optimization of Networks-on-Chip for Future Heterogeneous Systems-on-Chip

Due to the tight power budget and reduced time-to-market, Systems-on-Chip (SoC) have emerged as a power-efficient solution that provides the functionality required by target applications in embedded systems. To support a diverse set of applications such as real-time video/audio processing and sensor signal processing, SoCs consist of multiple heterogeneous components, such as software processors, digital signal processors, and application-specific hardware accelerators. These components offer different flexibility, power, and performance values so that SoCs can be designed by mix-and-matching them. With the increased amount of heterogeneous cores, however, the traditional interconnects in an SoC exhibit excessive power dissipation and poor performance scalability. As an alternative, Networks-on-Chip (NoC) have been proposed. NoCs provide modularity at design-time because communications among the cores are isolated from their computations via standard interfaces. NoCs also exploit communication parallelism at run-time because multiple data can be transferred simultaneously. In order to construct an efficient NoC, the communication behaviors of various heterogeneous components in an SoC must be considered with the large amount of NoC design parameters. Therefore, providing an efficient NoC design and optimization framework is critical to reduce the design cycle and address the complexity of future heterogeneous SoCs. This is the thesis of my dissertation. Some existing design automation tools for NoCs support very limited degrees of automation that cannot satisfy the requirements of future heterogeneous SoCs. First, these tools only support a limited number of NoC design parameters. Second, they do not provide an integrated environment for software-hardware co-development. Thus, I propose FINDNOC, an integrated framework for the generation, optimization, and validation of NoCs for future heterogeneous SoCs. The proposed framework supports software-hardware co-development, incremental NoC design-decision model, SystemC-based NoC customization and generation, and fast system protyping with FPGA emulations. Virtual channels (VC) and multiple physical (MP) networks are the two main alternative methods to provide better performance, support quality-of-service, and avoid protocol deadlocks in packet-switched NoC design. To examine the effect of using VCs and MPs with other NoC architectural parameters, I completed a comprehensive comparative analysis that combines an analytical model, synthesis-based designs for both FPGAs and standard-cell libraries, and system-level simulations. Based on the results of this analysis, I developed VENTTI, a design and simulation environment that combines a virtual platform (VP), a NoC synthesis tool, and four NoC models characterized at different abstraction levels. VENTTI facilitates an incremental decision-making process with four NoC abstraction models associated with different NoC parameters. The selected NoC parameters can be validated by running simulations with the corresponding model instantiated in the VP. I augmented this framework to complete FINDNOC by implementing ICON, a NoC generation and customization tool that dynamically combines and customizes synthesizable SystemC components from a predesigned library. Thanks to its flexibility and automatic network interface generation capabilities, ICON can generate a rich variety of NoCs that can be then integrated into any Embedded Scalable Platform (ESP) architectures for fast prototying with FPGA emulations. I designed FINDNOC in a modular way that makes it easy to augmenting it with new capabilities. This, combined with the continuous progress of the ESP design methodology, will provide a seamless SoC integration framework, where the hardware accelerators, software applications, and NoCs can be designed, validated, and integrated simultaneously, in order to reduce the design cycle of future SoC platforms

Smart vest for respiratory rate monitoring of COPD patients based on non-contact capacitive sensing

In this paper, a first approach to the design of a portable device for non-contact monitoring of respiratory rate by capacitive sensing is presented. The sensing system is integrated into a smart vest for an untethered, low-cost and comfortable breathing monitoring of Chronic Obstructive Pulmonary Disease (COPD) patients during the rest period between respiratory rehabilitation exercises at home. To provide an extensible solution to the remote monitoring using this sensor and other devices, the design and preliminary development of an e-Health platform based on the Internet of Medical Things (IoMT) paradigm is also presented. In order to validate the proposed solution, two quasi-experimental studies have been developed, comparing the estimations with respect to the golden standard. In a first study with healthy subjects, the mean value of the respiratory rate error, the standard deviation of the error and the correlation coefficient were 0.01 breaths per minute (bpm), 0.97 bpm and 0.995 (p < 0.00001), respectively. In a second study with COPD patients, the values were -0.14 bpm, 0.28 bpm and 0.9988 (p < 0.0000001), respectively. The results for the rest period show the technical and functional feasibility of the prototype and serve as a preliminary validation of the device for respiratory rate monitoring of patients with COPD.Ministerio de Ciencia e Innovación PI15/00306Ministerio de Ciencia e Innovación DTS15/00195Junta de Andalucía PI-0010-2013Junta de Andalucía PI-0041-2014Junta de Andalucía PIN-0394-201

Towards a Scalable Hardware/Software Co-Design Platform for Real-time Pedestrian Tracking Based on a ZYNQ-7000 Device

Currently, most designers face a daunting task to research different design flows and learn the intricacies of specific software from various manufacturers in hardware/software co-design. An urgent need of creating a scalable hardware/software co-design platform has become a key strategic element for developing hardware/software integrated systems. In this paper, we propose a new design flow for building a scalable co-design platform on FPGA-based system-on-chip. We employ an integrated approach to implement a histogram oriented gradients (HOG) and a support vector machine (SVM) classification on a programmable device for pedestrian tracking. Not only was hardware resource analysis reported, but the precision and success rates of pedestrian tracking on nine open access image data sets are also analysed. Finally, our proposed design flow can be used for any real-time image processingrelated products on programmable ZYNQ-based embedded systems, which benefits from a reduced design time and provide a scalable solution for embedded image processing products