A Deterministic Analysis of Decimation for Sigma-Delta Quantization of Bandlimited Functions

We study Sigma-Delta ($\Sigma\Delta$) quantization of oversampled bandlimited functions. We prove that digitally integrating blocks of bits and then down-sampling, a process known as decimation, can efficiently encode the associated $\Sigma\Delta$ bit-stream. It allows a large reduction in the bit-rate while still permitting good approximation of the underlying bandlimited function via an appropriate reconstruction kernel. Specifically, in the case of stable $r$th order $\Sigma\Delta$ schemes we show that the reconstruction error decays exponentially in the bit-rate. For example, this result applies to the 1-bit, greedy, first-order $\Sigma\Delta$ scheme

Optimal design of discrete-time delta sigma modulators

In this thesis, optimal signal transfer functions (STFs) and noise transfer functions (NTFs) for discrete time delta sigma (ΔΣ) modulators are determined. For a given oversampling rate (OSR), these STFs and NTFs are optimized with respect to a weighted combination of the ΔΣ modulator\u27s signal-to-noise ratio (SNR) and dynamic range (DR). This optimization problem is solved using a novel hybrid orthogonal genetic (HOG) algorithm that uses customized genetic operators to improve algorithm performance and accuracy when applied to multimodal, non-differentiable performance surfaces. To generate optimal system functions, the HOG algorithm is implemented as a constrained global optimizer to minimize cost functions which represent approximations of the system functions

Time-encoding analog-to-digital converters : bridging the analog gap to advanced digital CMOS? Part 2: architectures and circuits

The scaling of CMOS technology deep into the nanometer range has created challenges for the design of highperformance analog ICs: they remain large in area and power consumption in spite of process scaling. Analog circuits based on time encoding [1], [2], where the signal information is encoded in the waveform transitions instead of its amplitude, have been developed to overcome these issues. While part one of this overview article [3] presented the basic principles of time encoding, this follow-up article describes and compares the main time-encoding architectures for analog-to-digital converters (ADCs) and discusses the corresponding design challenges of the circuit blocks. The focus is on structures that avoid, as much as possible, the use of traditional analog blocks like operational amplifiers (opamps) or comparators but instead use digital circuitry, ring oscillators, flip-flops, counters, an so on. Our overview of the state of the art will show that these circuits can achieve excellent performance. The obvious benefit of this highly digital approach to realizing analog functionality is that the resulting circuits are small in area and more compatible with CMOS process scaling. The approach also allows for the easy integration of these analog functions in systems on chip operating at "digital" supply voltages as low as 1V and lower. A large part of the design process can also be embedded in a standard digital synthesis flow