Chaos synchronization of the master-slave generalized Lorenz systems via linear state error feedback control

This paper provides a unified method for analyzing chaos synchronization of the generalized Lorenz systems. The considered synchronization scheme consists of identical master and slave generalized Lorenz systems coupled by linear state error variables. A sufficient synchronization criterion for a general linear state error feedback controller is rigorously proven by means of linearization and Lyapunov's direct methods. When a simple linear controller is used in the scheme, some easily implemented algebraic synchronization conditions are derived based on the upper and lower bounds of the master chaotic system. These criteria are further optimized to improve their sharpness. The optimized criteria are then applied to four typical generalized Lorenz systems, i.e. the classical Lorenz system, the Chen system, the Lv system and a unified chaotic system, obtaining precise corresponding synchronization conditions. The advantages of the new criteria are revealed by analytically and numerically comparing their sharpness with that of the known criteria existing in the literature.Comment: 61 pages, 15 figures, 1 tabl

PVT-Robust CMOS Programmable Chaotic Oscillator: Synchronization of Two 7-Scroll Attractors

Designing chaotic oscillators using complementary metal-oxide-semiconductor (CMOS) integrated circuit technology for generating multi-scroll attractors has been a challenge. That way, we introduce a current-mode piecewise-linear (PWL) function based on CMOS cells that allow programmable generation of 2–7-scroll chaotic attractors. The mathematical model of the chaotic oscillator designed herein has four coefficients and a PWL function, which can be varied to provide a high value of the maximum Lyapunov exponent. The coefficients are implemented electronically by designing operational transconductance amplifiers that allow programmability of their transconductances. Design simulations of the chaotic oscillator are provided for the 0.35μ m CMOS technology. Post-layout and process–voltage–temperature (PVT) variation simulations demonstrate robustness of the multi-scroll chaotic attractors. Finally, we highlight the synchronization of two seven-scroll attractors in a master–slave topology by generalized Hamiltonian forms and observer approach. Simulation results show that the synchronized CMOS chaotic oscillators are robust to PVT variations and are suitable for chaotic secure communication applications.Universidad Autónoma de Tlaxcala CACyPI-UATx-2017Program to Strengthen Quality in Educational Institutions C/PFCE-2016-29MSU0013Y-07-23National Council for Science and Technology 237991 22284

A Software-based Low-Jitter Servo Clock for Inexpensive Phasor Measurement Units

This paper presents the design and the implementation of a servo-clock (SC) for low-cost Phasor Measurement Units (PMUs). The SC relies on a classic Proportional Integral (PI) controller, which has been properly tuned to minimize the synchronization error due to the local oscillator triggering the on-board timer. The SC has been implemented into a PMU prototype developed within the OpenPMU project using a BeagleBone Black (BBB) board. The distinctive feature of the proposed solution is its ability to track an input Pulse-Per-Second (PPS) reference with good long-term stability and with no need for specific on-board synchronization circuitry. Indeed, the SC implementation relies only on one co-processor for real-time application and requires just an input PPS signal that could be distributed from a single substation clock

Improving practical sensitivity of energy optimized wake-up receivers: proof of concept in 65nm CMOS

We present a high performance low-power digital base-band architecture, specially designed for an energy optimized duty-cycled wake-up receiver scheme. Based on a careful wake-up beacon design, a structured wake-up beacon detection technique leads to an architecture that compensates for the implementation loss of a low-power wake-up receiver front-end at low energy and area costs. Design parameters are selected by energy optimization and the architecture is easily scalable to support various network sizes. Fabricated in 65nm CMOS, the digital base-band consumes 0.9uW (V_DD=0.37V) in sub-threshold operation at 250kbps, with appropriate 97% wake-up beacon detection and 0.04% false alarm probabilities. The circuit is fully functional at a minimum V_DD of 0.23V at f_max=5kHz and 0.018uW power consumption. Based on these results we show that our digital base-band can be used as a companion to compensate for front-end implementation losses resulting from the limited wake-up receiver power budget at a negligible cost. This implies an improvement of the practical sensitivity of the wake-up receiver, compared to what is traditionally reported.Comment: Submitted to IEEE Sensors Journa

Dynamics estimation and generalized tuning of stationary frame current controller for grid-tied power converters

The integration of AC-DC power converters to manage the connection of generation to the grid has increased exponentially over the last years. PV or wind generation plants are one of the main applications showing this trend. High power converters are increasingly installed for integrating the renewables in a larger scale. The control design for these converters becomes more challenging due to the reduced control bandwidth and increased complexity in the grid connection filter. A generalized and optimized control tuning approach for converters becomes more favored. This paper proposes an algorithm for estimating the dynamic performance of the stationary frame current controllers, and based on it a generalized and optimized tuning approach is developed. The experience-based specifications of the tuning inputs are not necessary through the tuning approach. Simulation and experimental results in different scenarios are shown to evaluate the proposal.Peer ReviewedPostprint (published version