Low-Jitter Clock Multiplication: a Comparioson between PLLs and DLLs

This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output jitter of the architectures, due to the most important noise sources, is presented. Then, another important source of jitter in a DLL-based clock multiplier is treated, namely the stochastic mismatch in the delay cells which compose the DLL voltage-controlled delay line (VCDL). An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. A circuit design technique, called impedance level scaling, is then presented which allows the designer to optimize the noise and mismatch behavior of a circuit, independently from other specifications such as speed and linearity. Applying this technique on a delay cell design yields a direct tradeoff between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage

Hardware implantation of phased locked loop in biomedical diagnostics devices

Данная работа посвящена реализации синхронного демодулятора амплитудно-модулированных сигналов средствами цифровой обработки сигналов для повышения объема диагностической информации биомедицинских устройств. Особенностью реализуемого демодулятора является применение системы фазовой автоподстройки частоты (ФАПЧ), которая обеспечивая высокую чувствительность детектора, позволяет обрабатывать сигналы с малой мощностью. Для создания математической модели разрабатываемого демодулятора была составлена структурная схема ФАПЧ. При построении структурной схемы модели ФАПЧ, состоящая в данном случае из управляемого косинус-синусный генератора и петлевого фильтра учитывалось, что они работают в дискретном времени т. е. реализация этих схем будет выполнена полностью в цифровом виде. В результате расчета была получена передаточная характеристика и разностное уравнение петлевого фильтра (пропорционально-интегрирующего типа) для ФАПЧ второго порядка, а далее проведено имитационное моделирование рассчитанной системы ФАПЧ в приложении Simulink в пакете MatLab. Используя полученные формулы была написана программа для определения таких коэффициентов передачи петлевого фильтра, которые смогут обеспечить номинальную работу систему ФАПЧ. Полученные результаты имитационного моделирования подтвердили, что разработанный вариант петлевого фильтра обеспечивает широкую полосу захвата при одновременном подавлении дрожания фазы. Далее была составлена программа на языке Verilog c целью натурной реализации спроектированного демодулятора на основе программируемой логической интегральной схемы Xilinx серии Spartan 6 в системе проектирования Xilinx ISE. С целью верификации разработанного программного кода аппаратной реализации демодулятора в системе проектирования Xilinx ISE была проведена программная симуляцию входного сигналу в Testbench с одновременным использованием приложения ISIM, а визуализацию результатов симуляции - в GTKWave. Полученные экспериментальные результаты синтезированного демодулятора подтвердили результаты имитационного моделирования.This paper is devoted to the implementation of synchronous demodulator of amplitude-modulated signals by means of digital signal processing to increase the amount of diagnostic information of biomedical devices. A feature of the implemented demo-dulator is the usage of a phase-locked loop system, which, while ensuring high sensitivity of the demodulator, allows processing signals with low power. To create a mathematical model of the demodulator being developed, a phase-locked loop structure chart was drawn up. When drawing up a block diagram of the PLL model, which in this case consists of a numerically controlled cosine-sine oscillator and a loop filter, it was taken into account that they operate in discrete time, i. e. the implementation of these schemes will be performed entirely in digital form. As a result of the calculation, the transfer characteristic and difference equation of the loop filter (proportional-integrating type) for second-order of phase-locked loop were obtained, and then the simulation of the calculated phase-locked loop system was carried out in the Simulink application in MatLab. Using the formulas obtained, a program was written to determine such loop transfer coefficients that can ensure the nominal operation of the phase-locked loop. The obtained simulation results confirmed that the developed version of the loop filter provides a wide capture band while simultaneously suppressing phase jitter. At the next step, a computer program was compiled in the Verilog language with the purpose of the full-scale implementation of the designed demodulator based on the field-programmable gate arrayt debugging board such as Spartan 6 Xil-inx with the Xilinx ISE design system. In order to verify the developed software code for the hardware implementation of the demod-ulator in the Xilinx ISE design system, a software simulation of the input signal in Testbench with simultaneous use of the I SIM application was performed, and the simulation results were visualized in GTKWave. The obtained experimental results of the synthesized demodulator confirmed the results of simulation modeling

Design and Implementation of FPGA based linear All Digital Phase-Locked Loop for Signal Processing Applications

This project presents a linear all-digital phase locked loop based on FPGA. In this ADPLL the phase detection system is realized by generating an analytic signal using a compact implementation of Hilbert transform and then simply computing the instantaneous phase using CORDIC algorithm in vectoring mode of operation. A 16-bit pipelined CORDIC algorithm is employed in order to obtain the phase information of the signal. All the components used in this phase detection system are realized as digital discrete time components. This design does not involve any class of multipliers thus reducing the complexity of the design. The loop filter of the ADPLL has been designed using PI controller which has a low pass behavior and is used to discard the higher order harmonics of the error signal. The CORDIC algorithm in its rotation mode of operation is used to compute sinusoidal values for the DDS. The ADPLL model has been implemented using Xilinx ISE 12.3 and ModelSim PE Student Edition 10.1a. The ADPLL model describes a novel method of implementation of CORDIC algorithm for the DDS system. This ADPLL model basically used for synchronization of closed loop RF control signals in a heavy ion particle accelerator can be implemented even in an ASIC which can be seen with a more general use for many a applications in the daily life

차량용 CIS Interface 를 위한 All-Digital Phase-Locked Loop 의 설계 및 분석

학위논문 (석사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2021. 2. 정덕균.This thesis presents design techniques for All-Digital Phase-Locked Loop (ADPLL) assisting the automotive CMOS image sensor (CIS) interface. To target Gear 3 of the automotive physical system, the proposed AD-PLL has a wide operation range, low RMS jitter, and high PVT tolerance characteristics. Detailed analysis of the loop dynamics and the noise analysis of AD-PLL are done by using Matlab and Verilog behavioral modeling simulation before an actual design. Based on that analysis, the optimal DLF gain configurations are yielded, and also, accurate output responses and performance are predictable. The design techniques to reduce the output RMS jitter are discussed thoroughly and utilized for actual implementation. The proposed AD-PLL is fabricated in the 40 nm CMOS process and occupies an effective area of 0.026 mm2. The PLL output clock pulses exhibit an RMS jitter of 827 fs at 2 GHz. The power dissipation is 5.8 mW at 2 GHz, where the overall supply voltage domain is 0.9 V excluding the buffer which is 1.1 V domain.본 논문에서는 자동차 CMOS 이미지 센서 (CIS) 인터페이스를 지원하 는 AD-PLL 을 제안한다. Automotive Physical 시스템의 Gear 3 를 지원하기 위해 제안된 AD-PLL 은 1.5 GHz 에서 3 GHz 의 동작 주파수를 가지며, 낮 은 RMS Jitter 및 PVT 변화에 대한 높은 둔감성을 갖는다. 설계에 앞서서 Matlab 및 Verilog Behavioral Simulation 을 통해 Loop system 의 역학에 대한 자세한 분석 및 AD-PLL 의 Noise 분석을 수행하였고, 이 분석을 기반으로 최적의 DLF gain 과 정확한 출력 응답 및 성능을 예측 할 수 있었다. 또한, 출력의 Phase Noise 와 RMS Jitter 를 줄이기 위한 설계 기법을 자세히 다루고 있으며 이를 실제 구현에 활용했다. 제안된 회로는 40 nm CMOS 공정으로 제작되었으며 Decoupling Cap 을 제외하고 0.026 mm2 의 유효 면적을 차지한다. 측정된 출력 Clock 신호의 RMS Jitter 값은 2 GHz 에서 827 fs 이며, 총 5.8 mW의 Power 를 소비한다. 이 때, 전체적인 공급 전압은 0.9 V 이며, Buffer 의 Power 만이 1.1 V 를 사용하 였다.ABSTRACT I CONTENTS II LIST OF FIGURES IV LIST OF TABLES VII CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2 BACKGROUND ON ALL-DIGITAL PLL 4 2.1 OVERVIEW 4 2.2 BUILDING BLOCKS OF AD-PLL 7 2.2.1 TIME-TO-DIGITAL CONVERTER 7 2.2.2 DIGITALLY-CONTROLLED OSCILLATOR 10 2.2.3 DIGITAL LOOP FILTER 13 2.2.4 DELTA-SIGMA MODULATOR 16 2.3 PHASE NOISE ANALYSIS OF AD-PLL 20 2.3.1 BASIC ASSUMPTION OF LINEAR ANALYSIS 20 2.3.2 NOISE SOURCES OF AD-PLL 21 2.3.3 EFFECTS OF LOOP DELAY ON AD-PLL 24 2.3.4 PHASE NOISE ANALYSIS OF PROPOSED AD-PLL 26 CHAPTER 3 DESIGN OF ALL-DIGITAL PLL 28 3.1 DESIGN CONSIDERATION 28 3.2 OVERALL ARCHITECTURE 30 3.3 CIRCUIT IMPLEMENTATION 32 3.3.1 PFD-TDC 32 3.3.2 DCO 37 3.3.3 DIGITAL BLOCK 43 3.3.4 LEVEL SHIFTING BUFFER AND DIVIDER 45 CHAPTER 4 MEASUREMENT AND SIMULATION RESULTS 52 4.1 DIE PHOTOMICROGRAPH 52 4.2 MEASUREMENT SETUP 54 4.3 TRANSIENT ANALYSIS 57 4.4 PHASE NOISE AND SPUR PERFORMANCE 59 4.4.1 FREE-RUNNING DCO 59 4.4.2 PLL PERFORMANCE 61 4.5 PERFORMANCE SUMMARY 65 CHAPTER 5 CONCLUSION 67 BIBLIOGRAPHY 68 초 록 72Maste

Digital tanlock loop architecture with no delay

This article proposes a new architecture for a digital tanlock loop which eliminates the time-delay block. The �=2 (rad) phase shift relationship between the two channels, which is generated by the delay block in the conventional timedelay digital tanlock loop (TDTL), is preserved using two quadrature sampling signals for the loop channels. The proposed system outperformed the original TDTL architecture, when both systems were tested with frequency shift keying input signal. The new system demonstrated better linearity and acquisition speed as well as improved noise performance compared with the original TDTL architecture. Furthermore, the removal of the time-delay block enables all processing to be digitally performed, which reduces the implementation complexity. Both the original TDTL and the new architecture without the delay block were modelled and simulated using ATLAB/Simulink. Implementation issues, including complexity and relation to simulation of both architectures, are also addressed

Quadrature Phase-Domain ADPLL with Integrated On-line Amplitude Locked Loop Calibration for 5G Multi-band Applications

5th generation wireless systems (5G) have expanded frequency band coverage with the low-band 5G and mid-band 5G frequencies spanning 600 MHz to 4 GHz spectrum. This dissertation focuses on a microelectronic implementation of CMOS 65 nm design of an All-Digital Phase Lock Loop (ADPLL), which is a critical component for advanced 5G wireless transceivers. The ADPLL is designed to operate in the frequency bands of 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz. Unique ADPLL sub-components include: 1) Digital Phase Frequency Detector, 2) Digital Loop Filter, 3) Channel Bank Select Circuit, and 4) Digital Control Oscillator. Integrated with the ADPLL is a 90-degree active RC-CR phase shifter with on-line amplitude locked loop (ALL) calibration to facilitate enhanced image rejection while mitigating the effects of fabrication process variations and component mismatch. A unique high-sensitivity high-speed dynamic voltage comparator is included as a key component of the active phase shifter/ALL calibration subsystem. 65nm CMOS technology circuit designs are included for the ADPLL and active phase shifter with simulation performance assessments. Phase noise results for 1 MHz offset with carrier frequencies of 600MHz, 2.4GHz, and 3.8GHz are -130, -122, and -116 dBc/Hz, respectively. Monte Carlo simulations to account for process variations/component mismatch show that the active phase shifter with ALL calibration maintains accurate quadrature phase outputs when operating within the frequency bands 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz

Field-programmable gate array-controlled sweep velocity-locked laser pulse generator

This manuscript reports a FPGA-controlled sweep velocity-locked laser pulse generator (SV-LLPG) design based on an all-digital phase-locked loop (ADPLL). A distributed feedback (DFB) laser with modulated injection current was used as a swept-frequency laser source. An open loop pre-distortion modulation waveform was calibrated using a feedback iteration method to initially improve frequency sweep linearity. An ADPLL control system was then implemented using a field programmed gate array (FPGA) to lock the output of a Mach–Zehnder interferometer that was directly proportional to laser sweep velocity to an on-board system clock. Using this system, linearly chirped laser pulses with a sweep bandwidth of 111.16 GHz were demonstrated. Further testing evaluating the sensing utility of the system was conducted. In this test, the SV-LLPG served as the swept laser source of an optical frequency domain reflectometry (OFDR) system was used to interrogate a sub-terahertz range fiber structure (sub-THz-FS) array. A static strain test was then conducted and linear sensor results were observed

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor