An Assessment of PIER Electric Grid Research 2003-2014 White Paper

This white paper describes the circumstances in California around the turn of the 21st century that led the California Energy Commission (CEC) to direct additional Public Interest Energy Research funds to address critical electric grid issues, especially those arising from integrating high penetrations of variable renewable generation with the electric grid. It contains an assessment of the beneficial science and technology advances of the resultant portfolio of electric grid research projects administered under the direction of the CEC by a competitively selected contractor, the University of California’s California Institute for Energy and the Environment, from 2003-2014

Register-transfer-level power profiling for system-on-chip power distribution network design and signoff

Abstract. This thesis is a study of how register-transfer-level (RTL) power profiling can help the design and signoff of power distribution network in digital integrated circuits. RTL power profiling is a method which collects RTL power estimation results to a single power profile which then can be analysed in order to find interesting time windows for specifying power distribution network design and signoff. The thesis starts with theory part. Complementary metal-oxide semiconductor (CMOS) inverter power dissipation is studied at first. Next, power distribution network structure and voltage drop problems are introduced. Voltage drop is demonstrated by using power distribution network impedance figures. Common on-chip power distribution network structure is introduced, and power distribution network design flow is outlined. Finally, decoupling capacitors function and impact on power distribution network impedance are thoroughly explained. The practical part of the thesis contains RTL power profiling flow details and power profiling flow results for one simulation case in one design block. Also, some methods of improving RTL power estimation accuracy are discussed and calibration with extracted parasitic is then used to get new set of power profiling time windows. After the results are presented, overall RTL power estimation accuracy is analysed and resulted time windows are compared to reference gate-level time windows. RTL power profiling result analysis shows that resulted time windows match the theory and RTL power profiling seems to be a promising method for finding time windows for power distribution network design and signoff.Rekisterisiirtotason tehoprofilointi järjestelmäpiirin tehonsiirtoverkon suunnittelussa ja verifioinnissa. Tiivistelmä. Tässä työssä tutkitaan, miten rekisterisiirtotason (RTL) tehoprofilointi voi auttaa digitaalisten integroitujen piirien tehonsiirtoverkon suunnittelussa ja verifioinnissa. RTL-tehoprofilointi on menetelmä, joka analysoi RTL-tehoestimoinnista saadusta tehokäyrästä hyödyllisiä aikaikkunoita tehonsiirtoverkon suunnitteluun ja verifiointiin. Työ alkaa teoriaosuudella, jonka aluksi selitetään, miten CMOS-invertteri kuluttaa tehoa. Seuravaksi esitellään tehonsiirtoverkon rakenne ja pahimmat tehonsiirtoverkon jännitehäviön aiheuttajat. Jännitehäviötä havainnollistetaan myös piirikaavioiden ja impedanssikäyrien avustuksella. Lisäksi integroidun piirin tehonsiirtoverkon suunnitteluvuo ja yleisin rakenne on esitelty. Lopuksi teoriaosuus käsittelee yksityiskohtaisesti ohituskondensaattoreiden toiminnan ja vaikutuksen tehonsiirtoverkon kokonaisimpedanssiin. Työn kokeellisessa osuudessa esitellään ensin tehoprofiloinnin vuo ja sen jälkeen vuon tulokset yhdelle esimerkkilohkolle yhdessä simulaatioajossa. Lisäksi tässä osiossa käsitellään RTL-tehoestimoinnin tarkkuutta ja tehdään RTL-tehoprofilointi loisimpedansseilla kalibroidulle RTL-mallille. Lopuksi RTL-tehoestimoinnin tuloksia ja saatuja RTL-tehoprofiloinnin aikaikkunoita analysoidaan ja verrataan porttitason mallin tuloksiin. RTL-tehoprofiloinnin tulosten analysointi osoittaa, että saatavat aikaikkunat vastaavat teoriaa ja että RTL-tehoprofilointi näyttää lupaavalta menetelmältä tehosiirtoverkon analysoinnin ja verifioinnin aikaikkunoiden löytämiseen

Belle II Technical Design Report

The Belle detector at the KEKB electron-positron collider has collected almost 1 billion Y(4S) events in its decade of operation. Super-KEKB, an upgrade of KEKB is under construction, to increase the luminosity by two orders of magnitude during a three-year shutdown, with an ultimate goal of 8E35 /cm^2 /s luminosity. To exploit the increased luminosity, an upgrade of the Belle detector has been proposed. A new international collaboration Belle-II, is being formed. The Technical Design Report presents physics motivation, basic methods of the accelerator upgrade, as well as key improvements of the detector.Comment: Edited by: Z. Dole\v{z}al and S. Un

Requirements to Testing of Power System Services Provided by DER Units

The present report forms the Project Deliverable ‘D 2.2’ of the DERlab NoE project, supported by the EC under Contract No. SES6-CT-518299 NoE DERlab. The present document discuss the power system services that may be provided from DER units and the related methods to test the services actually provided, both at component level and at system level

Conceptual design and analysis of a large antenna utilizing electrostatic membrane management

Conceptual designs and associated technologies for deployment 100 m class radiometer antennas were developed. An electrostatically suspended and controlled membrane mirror and the supporting structure are discussed. The integrated spacecraft including STS cargo bay stowage and development were analyzed. An antenna performance evaluation was performed as a measure of the quality of the membrane/spacecraft when used as a radiometer in the 1 GHz to 5 GHz region. Several related LSS structural dynamic models differing by their stiffness property (and therefore, lowest modal frequencies) are reported. Control system whose complexity varies inversely with increasing modal frequency regimes are also reported. Interactive computer-aided-design software is discussed

Novel Front-end Electronics for Time Projection Chamber Detectors

Este trabajo ha sido realizado en la Organización Europea para la Investigación Nuclear (CERN) y forma parte del proyecto de investigación Europeo para futuros aceleradores lineales (EUDET). En física de partículas existen diferentes categorías de detectores de partículas. El diseño presentado esta centrado en un tipo particular de detector de trayectoria de partículas denominado TPC (Time Projection Chamber) que proporciona una imagen en tres dimensiones de las partículas eléctricamente cargadas que atraviesan su volumen gaseoso. La tesis incluye un estudio de los objetivos para futuros detectores, resumiendo los parámetros que un sistema de adquisición de datos debe cumplir en esos casos. Además, estos requisitos son comparados con los actuales sistemas de lectura utilizados en diferentes detectores TPC. Se concluye que ninguno de los sistemas cumple las restrictivas condiciones. Algunos de los principales objetivos para futuros detectores TPC son un altísimo nivel de integración, incremento del número de canales, electrónica más rápida y muy baja potencia. El principal inconveniente del estado del arte de los sistemas anteriores es la utilización de varios circuitos integrados en la cadena de adquisición. Este hecho hace imposible alcanzar el altísimo nivel de integración requerido para futuros detectores. Además, un aumento del número de canales y frecuencia de muestreo haría incrementar hasta valores no permitidos la potencia utilizada. Y en consecuencia, incrementar la refrigeración necesaria (en caso de ser posible). Una de las novedades presentadas es la integración de toda la cadena de adquisición (filtros analógicos de entrada, conversor analógico-digital (ADC) y procesado de señal digital) en un único circuito integrado en tecnología de 130nm. Este chip es el primero que realiza esta altísima integración para detectores TPC. Por otro lado, se presenta un análisis detallado de los filtros de procesado de señal. Los objetivos más importantes es la reduccióGarcía García, EJ. (2012). Novel Front-end Electronics for Time Projection Chamber Detectors [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/16980Palanci

Wide-area backup protection and protection performance analysis scheme using PMU data

This paper presents a wide-area backup protection scheme that incorporates protection performance analysis based solely on voltage from Phasor Measurement Units (PMUs). The system reports and summarizes information relating to fault detection, and identification of the faulted circuit(s) protection/circuit breaker operation (i.e. whether it is correct or not), in a short period of time. It can also be applied as an effective and relatively simple, fast, wide-area backup protection to improve the resilience of power systems. Case studies are presented, where the proposed wide-area backup protection scheme is validated using the IEEE 14-bus network. It is demonstrated that the proposed scheme is capable of correctly detecting faults (including high-resistance faults) in less than 100 ms from fault inception and can report on whether the protection/circuit breakers have operated as expected within a further 100 ms, thereby coordinating with existing protection systems with a view to enhancing the system reliability and security by appending existing protection systems with system-wide information. Applicability of the developed system to large-scale power systems is also demonstrated. Discussion relating to how this method can be cost effective through exploitation of existing PMU data, which may already be used for other purposes, is included

Photovoltaic stand-alone modular systems, phase 2

The final hardware and system qualification phase of a two part stand-alone photovoltaic (PV) system development is covered. The final design incorporated modular, power blocks capable of expanding incrementally from 320 watts to twenty kilowatts (PK). The basic power unit (PU) was nominally rated 1.28 kWp. The controls units, power collection buses and main lugs, electrical protection subsystems, power switching, and load management circuits are housed in a common control enclosure. Photo-voltaic modules are electrically connected in a horizontal daisy-chain method via Amp Solarlok plugs mating with compatible connectors installed on the back side of each photovoltaic module. A pair of channel rails accommodate the mounting of the modules into a frameless panel support structure. Foundations are of a unique planter (tub-like) configuration to allow for world-wide deployment without restriction as to types of soil. One battery string capable of supplying approximately 240 ampere hours nominal of carryover power is specified for each basic power unit. Load prioritization and shedding circuits are included to protect critical loads and selectively shed and defer lower priority or noncritical power demands. The baseline system, operating at approximately 2 1/2 PUs (3.2 kW pk.) was installed and deployed. Qualification was successfully complete in March 1983; since that time, the demonstration system has logged approximately 3000 hours of continuous operation under load without major incident