Conception d'un réseau de plots configurables multifonctions analogiques et numériques combiné à un réseau de distribution de puissance intégrés à l'échelle de la tranche de silicium

RÉSUMÉ De nos jours, les systèmes électroniques sont en constante croissance en taille et en complexité. Cette complexité combinée à la réduction du temps de mise en marché rendant le design de systèmes électroniques un grand défi pour les designers. Une plateforme de prototypage a récemment été introduite afin de s’attaquer toutes ces contraintes à la fois. Cette plateforme s’appuie sur l’implémentation d’un circuit configurable à l’échelle d’une tranche de silicium complète de 200mm de diamètre. Cette surface est recouverte d’une mer de plots conducteurs configurables appelés NanoPads. Ces NanoPads sont suffisamment petits pour supporter des billes d’un diamètre de 250 μm et d’un espacement de 500 μm et sont regroupés en matrices de 4×4 pour former des Cellules, qui sont à leur tour assemblées en Réticules de 32×32. Ces Réticules sont ensuite photo-répétés sur toute la surface d’une tranche de silicium et sont interconnectés entre eux pour former le WaferIC. Cet arrangement particulier de plots conducteurs configurables permet à un usager de déposer sur la surface active du WaferIC les circuits intégrés constituant un système électronique, sans tenir en compte l’orientation spatiale de ces derniers, de créer un schéma d’interconnexions, de distribution la puissance et de débuter le prototypage du système en question. Une version préliminaire a été fabriquées et testées avec succès et permet d’alimenter des circuits -intégrés et de configurer le WaferIC pour les interconnecter. Cette thèse par articles présente une nouvelle version du WaferIC avec une nouvelle proposition de distribution de la puissance avec une approche de maîtres-esclaves qui met en valeur l’utilisation de plusieurs rails d’alimentation afin d’améliorer le rendement énergétique. Il est également mis de l’avant un réseau très dense de convertisseurs analogique-numérique (CAN) et numérique-analogique (CNA) de plus de 300k éléments, tolérant aux défectuosités et aux défauts de fabrication. Ce réseau de CAN-CNA permet d’améliorer le WaferIC avec la transmission de signaux analogiques, en plus des signaux numériques. Ce manuscrit comporte trois articles : un publié chez « Springer Science & Business Media Analog Integrated Circuits and Signal Processing », un publié chez « IEEE Transactions on Circuits and Systems I : Regular Papers » et finalement un soumis chez « IEEE Transactions on Very Large Scale Integration ».----------ABSTRACT Nowadays, electronic systems are in constant growth, size and complexity; combined with time to market it makes a challenge for electronic system designers. A prototyping platform has been recently introduced and addresses all those constraints at once. This platform is based on an active 200 mm in diameter wafer-scale circuit, which is covered with a set of small configurable and conductive pads called NanoPads. These NanoPads are designed to be small enough to support any integrated-circuit μball of a 250 μm diameter and 500 μm of pitch. They are assembled in a 4×4 matrix, forming a Unit-Cell, which are grouped in a Reticle-Image of 32×32. These Reticle-Images are photo-repeated over the entire surface of a 200 mm in diameter wafer and are interconnected together using interreticle stitching. This active wafer-scale circuit is called a WaferIC. This particular topology and distribution of NanoPads allows an electronic system designer to manually deposit any integrated-circuit (IC) on the active alignment insensitive surface of the WaferIC, to build the netlist linking all the ICs, power-up the systems and start the prototyping of the system. In this manuscript-based thesis, we present an improved version of the WaferIC with a novel approach for the power distribution network with a master-slave topology, which makes the use of embedded dual-power-rail voltage regulators in order to improve the power efficiency and decrease thermal dissipation. We also propose a default-tolerant network of analog to digital (ADC) and digital to analog (DAC) converters of more than 300k. This ADC-DAC network allows the WaferIC to not only support digital ICs but also propagate analog signals from one NanoPad to another. This thesis includes 3 papers : one submission to "Springer Science & Business Media Analog Integrated Circuits and Signal Processing", one submission to "IEEE Transactions on Circuits and Systems I : Regular Papers" and finally one submission to "IEEE Transactions on Very Large-Scale Integration". These papers propose novel architectures of dualrail voltage regulators, configurable analog buffers and configurable voltage references, which can be used as a DAC. A novel approach for a power distribution network and the integration of all the presented architectures is also proposed with the fabrication of a testchip in CMOS 0.18 μm technology, which is a small-scale version of the WaferIC

Potential and Challenges of Analog Reconfigurable Computation in Modern and Future CMOS

In this work, the feasibility of the floating-gate technology in analog computing platforms in a scaled down general-purpose CMOS technology is considered. When the technology is scaled down the performance of analog circuits tends to get worse because the process parameters are optimized for digital transistors and the scaling involves the reduction of supply voltages. Generally, the challenge in analog circuit design is that all salient design metrics such as power, area, bandwidth and accuracy are interrelated. Furthermore, poor flexibility, i.e. lack of reconfigurability, the reuse of IP etc., can be considered the most severe weakness of analog hardware. On this account, digital calibration schemes are often required for improved performance or yield enhancement, whereas high flexibility/reconfigurability can not be easily achieved. Here, it is discussed whether it is possible to work around these obstacles by using floating-gate transistors (FGTs), and analyze problems associated with the practical implementation. FGT technology is attractive because it is electrically programmable and also features a charge-based built-in non-volatile memory. Apart from being ideal for canceling the circuit non-idealities due to process variations, the FGTs can also be used as computational or adaptive elements in analog circuits. The nominal gate oxide thickness in the deep sub-micron (DSM) processes is too thin to support robust charge retention and consequently the FGT becomes leaky. In principle, non-leaky FGTs can be implemented in a scaled down process without any special masks by using “double”-oxide transistors intended for providing devices that operate with higher supply voltages than general purpose devices. However, in practice the technology scaling poses several challenges which are addressed in this thesis. To provide a sufficiently wide-ranging survey, six prototype chips with varying complexity were implemented in four different DSM process nodes and investigated from this perspective. The focus is on non-leaky FGTs, but the presented autozeroing floating-gate amplifier (AFGA) demonstrates that leaky FGTs may also find a use. The simplest test structures contain only a few transistors, whereas the most complex experimental chip is an implementation of a spiking neural network (SNN) which comprises thousands of active and passive devices. More precisely, it is a fully connected (256 FGT synapses) two-layer spiking neural network (SNN), where the adaptive properties of FGT are taken advantage of. A compact realization of Spike Timing Dependent Plasticity (STDP) within the SNN is one of the key contributions of this thesis. Finally, the considerations in this thesis extend beyond CMOS to emerging nanodevices. To this end, one promising emerging nanoscale circuit element - memristor - is reviewed and its applicability for analog processing is considered. Furthermore, it is discussed how the FGT technology can be used to prototype computation paradigms compatible with these emerging two-terminal nanoscale devices in a mature and widely available CMOS technology.Siirretty Doriast

Advanced Applications of Rapid Prototyping Technology in Modern Engineering

Rapid prototyping (RP) technology has been widely known and appreciated due to its flexible and customized manufacturing capabilities. The widely studied RP techniques include stereolithography apparatus (SLA), selective laser sintering (SLS), three-dimensional printing (3DP), fused deposition modeling (FDM), 3D plotting, solid ground curing (SGC), multiphase jet solidification (MJS), laminated object manufacturing (LOM). Different techniques are associated with different materials and/or processing principles and thus are devoted to specific applications. RP technology has no longer been only for prototype building rather has been extended for real industrial manufacturing solutions. Today, the RP technology has contributed to almost all engineering areas that include mechanical, materials, industrial, aerospace, electrical and most recently biomedical engineering. This book aims to present the advanced development of RP technologies in various engineering areas as the solutions to the real world engineering problems

Combining SOA and BPM Technologies for Cross-System Process Automation

This paper summarizes the results of an industry case study that introduced a cross-system business process automation solution based on a combination of SOA and BPM standard technologies (i.e., BPMN, BPEL, WSDL). Besides discussing major weaknesses of the existing, custom-built, solution and comparing them against experiences with the developed prototype, the paper presents a course of action for transforming the current solution into the proposed solution. This includes a general approach, consisting of four distinct steps, as well as specific action items that are to be performed for every step. The discussion also covers language and tool support and challenges arising from the transformation

NASA Tech Briefs, February 1994

Topics covered include: Test and Measurement; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery; Fabrication Technology; Mathematics and Information Sciences; Life Sciences; Books and Report

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers

Hybrid approaches to quantum information using ions, atoms and photons

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Physics, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 235-250).This thesis presents two hybrid systems for quantum information processing - one joining cold ions and cold atoms and another coupling linear chains of atomic ions with photons via an optical resonator. The first experimental realization of a hybrid cold-ion / cold-atom system is presented in the form of Yb atoms trapped in a magneto-optical trap overlapped with Yb+ ions stored in a radio-frequency (RF) planar Paul trap. The overlap between the excited MOT atoms and the ion trap is used to obtain isotope-selective ion trap loading rates 104 times higher than previously achieved. The interaction between atoms and ions is measured by observing near-resonant charge-exchange collisions between Yb and Yb+ with a collision rate matching the classical Langevin cross-section. Momentum transfer between cold atoms and cold ions is observed via collisions of Yb+ ions with laser-cooled Rb atoms and a classical limit to the ion-atom collision energy in RF traps derived, with relevance to current ion experiments. The second part of the thesis presents the first integration of a scalable, microfabricated surface ion trap chip with an optical resonator. This chip trap is used to produce a linear array of ion traps and load these traps with isotopically-selected chains of Yb+ ions. The ion chains are overlapped with the mode of an optical resonator and the coupling of the individual ions to the resonator mode demonstrated by recording the frequency spectrum of the ions' near-resonance fluorescence. These measurements demonstrate the capability of the present system to store and process quantum information stored in short ion chains and to communicate this information via photons, with applications to large-scale trapped ion quantum information processing. The strong-near resonant optical field available inside the optical resonator may also be used to produce a periodic optical potential for trapped ions, with applications to quantum simulation.by Marko Cetina.Ph.D

Understanding Quantum Technologies 2022

Understanding Quantum Technologies 2022 is a creative-commons ebook that provides a unique 360 degrees overview of quantum technologies from science and technology to geopolitical and societal issues. It covers quantum physics history, quantum physics 101, gate-based quantum computing, quantum computing engineering (including quantum error corrections and quantum computing energetics), quantum computing hardware (all qubit types, including quantum annealing and quantum simulation paradigms, history, science, research, implementation and vendors), quantum enabling technologies (cryogenics, control electronics, photonics, components fabs, raw materials), quantum computing algorithms, software development tools and use cases, unconventional computing (potential alternatives to quantum and classical computing), quantum telecommunications and cryptography, quantum sensing, quantum technologies around the world, quantum technologies societal impact and even quantum fake sciences. The main audience are computer science engineers, developers and IT specialists as well as quantum scientists and students who want to acquire a global view of how quantum technologies work, and particularly quantum computing. This version is an extensive update to the 2021 edition published in October 2021.Comment: 1132 pages, 920 figures, Letter forma

Cryogenic technologies for scalable trapped ion quantum computing

There has been a great deal of effort and progress made towards building a fully scalable quantum computer but there are still significant engineering challenges to overcome. Trapped ions currently represent the best fundamental technology towards achieving this goal and so they form the basis for the work in this thesis. In this thesis I describe the work towards creating a closed cycle cryogenic vacuum system driven by a Gifford McMahon cryogenic cooler. I will show the equipment required to trap a Ytterbium 174/171 ion on a cryogenic surface ion trap. The primary goal is to create a fast turn-around system for ion trap research. Room temperature systems suffer from long baking times and as such ion traps are rarely changed, this means that there is little room for testing and comparing of trap designs and predicting optimum trapping parameters as each trap is usually not changed unless there is a fault. In the cryogenic system, every effort is made to make the system generic enough to allow for any trap design to be tested and to be replaced within 24 hours. To create reliable trapping parameters we require a toolkit that can numerically simulate the required RF and DC voltages used to trap the ions above the surface of the ion trap. There are many numerical methods that can be used (FEM, FVM, BEM, FTDI, etc) and in this thesis I describe multiple methods and what their relative benefits are. Since we want to create a full toolkit to allow for chip design and optimisation, most commercial programs suffer from inadequate API interfaces or they dictate which programming languages you can interface with. This would limit our abilities to develop and optimise trapping parameters, especially in a cryogenic system where the goal is rapid deployment. To this end I created a new toolkit based on the Scuff BEM solver engine that allows us to go from AutoCAD layout to field solver and gives us accurate field potentials that match micromotion compensated voltages to within 1%. I describe a novel cryogenic resonator built out of superconducting wire based on an auto-transformer topology, I compare its strengths and weaknesses compared to other technologies already in use for trapped ion research. I also describe a novel DSUB design with integrated modular filtering which allows for 50 connections per DSUB. This DSUB is used to connect two sets of 50 wires to a PCB for wirebonding to the surface trap. This allows me to save space within the 4k shield where other PCB designs would not fit. Also it is modular in design which allows for different cutoff frequencies to be swapped out as desired. I also describe different chip mounting technologies including epoxy based, physical clamping and indium foil based. After extensive testing the indium foil diebonded approach is deemed as being the most reliable and fastest non-destructive method. I also describe a novel cryogenic coil design for generating 12T m−1 field gradients for microwave based ion gates with Ytterbium 171. I then describe the creation of a combined RF and microwave antenna for delivering coherent RF and 12.6GHz microwave radiation inside the cryogenic environment. This design is much smaller than typical waveguide typologies used. I finish by showing the first trapped ions in a cryogenic surface ion trap in the UK and heating rate tests performed on two different linear surface traps. The first trap was a sapphire based, 150µm ion height linear trap with a measured heating rate of Se(1MHz) = 5.93(10) ∗ 10−14(V /m)2. The second ion trap is a 50k Silicon based, 100µm ion height linear trap with a measured heating rate of Se(1MHz) = 2.45(10)∗10−13(V /m)