Nano-intrinsic security primitives for internet of everything

With the advent of Internet-enabled electronic devices and mobile computer systems, maintaining data security is one of the most important challenges in modern civilization. The innovation of physically unclonable functions (PUFs) shows great potential for enabling low-cost low-power authentication, anti-counterfeiting and beyond on the semiconductor chips. This is because secrets in a PUF are hidden in the randomness of the physical properties of desirably identical devices, making it extremely difficult, if not impossible, to extract them. Hence, the basic idea of PUF is to take advantage of inevitable non-idealities in the physical domain to create a system that can provide an innovative way to secure device identities, sensitive information, and their communications. While the physical variation exists everywhere, various materials, systems, and technologies have been considered as the source of unpredictable physical device variation in large scales for generating security primitives. The purpose of this project is to develop emerging solid-state memory-based security primitives and examine their robustness as well as feasibility. Firstly, the author gives an extensive overview of PUFs. The rationality, classification, and application of PUF are discussed. To objectively compare the quality of PUFs, the author formulates important PUF properties and evaluation metrics. By reviewing previously proposed constructions ranging from conventional standard complementary metal-oxide-semiconductor (CMOS) components to emerging non-volatile memories, the quality of different PUFs classes are discussed and summarized. Through a comparative analysis, emerging non-volatile redox-based resistor memories (ReRAMs) have shown the potential as promising candidates for the next generation of low-cost, low-power, compact in size, and secure PUF. Next, the author presents novel approaches to build a PUF by utilizing concatenated two layers of ReRAM crossbar arrays. Upon concatenate two layers, the nonlinear structure is introduced, and this results in the improved uniformity and the avalanche characteristic of the proposed PUF. A group of cell readout method is employed, and it supports a massive pool of challenge-response pairs of the nonlinear ReRAM-based PUF. The non-linear PUF construction is experimentally assessed using the evaluation metrics, and the quality of randomness is verified using predictive analysis. Last but not least, random telegraph noise (RTN) is studied as a source of entropy for a true random number generation (TRNG). RTN is usually considered a disadvantageous feature in the conventional CMOS designs. However, in combination with appropriate readout scheme, RTN in ReRAM can be used as a novel technique to generate quality random numbers. The proposed differential readout-based design can maintain the quality of output by reducing the effect of the undesired noise from the whole system, while the controlling difficulty of the conventional readout method can be significantly reduced. This is advantageous as the differential readout circuit can embrace the resistance variation features of ReRAMs without extensive pre-calibration. The study in this thesis has the potential to enable the development of cost-efficient and lightweight security primitives that can be integrated into modern computer mobile systems and devices for providing a high level of security

Conversion analogique-numérique Sigma-Delta large bande appliquée à la mesure des non-linéarités des amplificateurs de puissance

Power amplifiers, which are essential elements of any communication system, will play a crucial role in the development of future communication systems. Today improving power amplifiers requires technological advances at the circuit device level, but one also must consider a more global approach. In particular, advances in digital processing can now correct in the early stage of the communication chain some distortions that are generated downstream in the chain. Digital pre-distortion is a correction technique for power amplifiers that has a growing interest because of its completely digital implementation and of its gains in linearity and energy consumption. This technique requires a feedback path where the analog-to-digital converter is a critical element. This component must satisfy the constraints of high resolution , wide bandwidth, and high linearity. In this thesis, we propose a new architecture of analog-to-digital converter based on bandpass Delta-Sigma modulators. This architecture takes advantage of operating bandpass modulators that are designed to work in parallel, each focusing on different frequencies, but also of a particular cascading arrangement to eliminate the useful signal, which has a high power, in order to reduce dynamics constraints. High-level design and simulations were carried out for discrete time and continuous time systems and also required the development of appropriate simulation tools.Les amplificateurs de puissance, éléments constitutifs essentiels de tout système de télécommunication, vont jouer un rôle capital dans le développement des futurs systèmes de communication. Aujourd'hui l'amélioration des amplificateurs de puissance nécessite un progrès technologique au niveau du composant lui même mais doit aussi tenir compte d'une approche plus globale. En particulier, le progrès dans les traitements numériques permet aujourd'hui de corriger en amont certaines distorsions qui seront générées en aval de la chaîne de communication. La pré-distorsion numérique est une technique de correction des amplificateurs de puissance qui connaît un intérêt grandissant de par son intégration complètement numérique et par les gains en linéarité et en consommation. Cette technique nécessite une voie de retour dont un élément critique est le convertisseur analogique-numérique. Ce composant doit répondre à des contraintes de résolution, de bande passante et de linéarité élevées. Dans cette thèse, nous proposons une nouvelle architecture de convertisseur analogique-numérique à base de modulateurs Sigma-Delta passe-bande. Cette architecture tire partie du fonctionnement passe bande des modulateurs que nous faisons travailler en parallèle, chacun centré sur différentes fréquences, mais aussi d'un agencement en cascade particulier pour éliminer le signal utile, qui est de forte puissance, dans le but de diminuer les contraintes de dynamique.La conception haut niveau et les simulations ont été menées pour des systèmes à temps discret et aussi à temps continu et a nécessité le développement d'outils adaptés de simulation se basant sur la boîte à outils Delta Sigma Toolbox de Richard Schreie

Compensação da não-linearidade do modulador-MZ-IQ baseada em FPGA

Mestrado em Engenharia Electrónica e TelecomunicaçõesNos últimos anos, a crescente necessidade de largura de banda e a evolução das técnicas de processamento digital de sinal renovaram o interesse pelos sistemas de comunicação ópticos coerentes. O modulador IQ assume-se como um componente chave nestes transmissores, sendo responsável pela conversão de informação do domínio eléctrico para o domínio óptico. Os moduladores Mach-Zehnder que constituem este dispositivo recebem sinais de drive com uma excursão controlada, garantindo a utilização de uma região aproximadamente linear das suas funções transferência e a geração de constelações sem distorções de fase. No entanto, existem vantagens em explorar a extensão completa da característica dos moduladores. Neste contexto, torna-se relevante efectuar um estudo acerca das técnicas de pré-distorção electrónica que permitem corrigir os efeitos das não-linearidades associadas a este método de transmissão. Esta dissertação foca-se no estudo da compensação dos impactos que a característica não-linear do modulador Mach-Zehnder tem nos sistemas de transmissão ópticos coerentes. Após a identificação e desenvolvimento de soluções matemáticas para o problema, realizaram-se vários testes utilizando um simulador integrado em ambiente MATLAB. Um sistema de transmissão coerente utilizando formatos de modulação QAM e os respectivos algoritmos de compensação foram posteriormente implementados em FPGA. Desenvolveram-se também co-simulações que permitiram garantir que o hardware concebido produzia os resultados desejados. Para além disso, realizaram-se vários testes utilizando um modulador IQ disponível no “Laboratório de Óptica” do Instituto de Telecomunicações de Aveiro. O objectivo consistiu em operar o sistema em condições laboratoriais e analisar o desempenho dos algoritmos de compensação em ambiente real.In recent years, the ever-increasing bandwidth demand and the evolution of digital signal processing techniques renewed the interest for the optical coherent systems. The IQ-Modulator is a key component in optical coherent transmitters, being responsible for the conversion of information from electrical to optical domain. The Mach-Zehnder modulators that compose this device receive driving signals with a controlled excursion, in order to use an approximately linear region of their transfer function and produce constellations without phase distortions. However, there are advantages in exploit the full range of the modulators’ characteristic. In this context, a study about the electronic predistortion techniques required to overcome the nonlinear effects associated to this transmission method becomes relevant. The subject of this dissertation is the compensation of impairments related to the nonlinear characteristic of the Mach-Zehnder Modulator in coherent optical transmission systems. After the identification and development of mathematical solutions for the problem, several tests were made using a simulator that runs in a MATLAB environment. A QAM coherent transmitter system and the compensation algorithm were then implemented in a FPGA platform. Co-simulations were performed in order to prove that the designed hardware was generating correct results. Furthermore, some tests were conducted using an IQ-Modulator available in the “Optics Laboratory” at Telecommunications Institute of Aveiro. The goal was to operate the system under laboratorial conditions and analyze the performance of the compensation algorithm in a real case scenario

Opportunities for radio frequency nanoelectronic integrated circuits using carbon-based technologies

This thesis presents a body of work on the modeling of and performance predictions for carbon nanotube field-effect transistors (CNFET) and graphene field-effect transistors (GFET). While conventional silicon-based CMOS is expected to reach its ultimate scaling limits during the next decade, these two novel technologies are promising candidates for future high-performance electronics. The main goal of this work is to investigate on the opportunities of using such carbon-based electronics for RF integrated circuits. This thesis addresses 1) the modeling of noise and process variability in CNFETs, 2) RF performance predictions for CNFETs, and 3) an accurate GFET compact model. This work proposes the first CNFET noise compact model. Noise is of primary importance for RF applications and its description significantly increases the insight gained from simulation studies. Furthermore, a CNFET variability model is presented, which handles tube synthesis and metal tube removal imperfections. These two model extensions have been added to the Stanford CNFET compact model and allow for the variability-aware RF performance assessment of the CNFET technology. In continuation, comprehensive RF performance projections for CNFETs are provided both on the device and circuit level. The overall set of ITRS RF-CMOS technology requirement FoMs is determined and shows that the CNFET performs excellently in terms of speed, gain, and minimum noise figure. Furthermore, for the first time FoMs are reported for the basic RF building blocks low-noise amplifier and oscillator. In addition, it is shown that CNFET downscaling yields significant performance improvements. Based on these analyses it is confirmed that the CNFET has the potential to outperform Si-CMOS in RF applications. A third key contribution of this thesis is the development of an accurate GFET compact model. Previous compact models simplify several physical aspects, which can cause erroneous simulation results. Here, an accurate yet simple mathematical description of the GFET’s current-voltage relation is proposed and implemented in Verilog-A. Comprehensive error analyses are done in order to highlight the advantages of the new approach. Furthermore, the model is verified against measurement results. The developed GFET model is an important step towards better understanding the characteristics and opportunities of graphene-based analog circuitry