Design of Quaternary Arithmetic Unit in Standard CMOS

The multiple-valued logic (MVL) plays very important role in VLSI circuit design. The number of interconnections is reduced by using Quaternary logic than binary logic. In this paper we present the design of a prototype implementation and experimental results. Quaternary converter circuits are designed by using down literal circuits (DLC). Addition, Subtraction and multiplication i.e. arithmetic operations in Modulo-4 and in galois field logic are design and simulation results are shown in this paper by using Quaternary logic. Schematic of the design is done through S-SPICE. Simulation result is shown in Tspice. Tanner has created a software platform that is cost-effective and easy to use. DOI: 10.17762/ijritcc2321-8169.15054

Review On High Performance Quaternary Arithmetic and Logical Unit in Standard CMOS

Arithmetic circuits play an important role in computational circuits. Multiple Valued Logic (MVL) provides higher density per integrated circuit area compared to traditional two valued binary logic. Quaternary (Four-valued) logic also provides easy interfacing to binary logic because radix 4(22) allows for the use of simple encoding/decoding circuits. The functional completeness is proved by a set of fundamental quaternary cells and the collection of cells based on the Supplementary Symmetrical Logic Circuit Structure (SUSLOC). Cells are designed, simulated, and used to build several quaternary fixed-point arithmetic circuits such as adders, multipliers etc. These SUSLOC circuit cells are validated using SPICE models and the arithmetic architectures are validated using System Verilog models for functional correctness. Quaternary (radix-4) dual operand encoding principles are applied to optimize power and performance of adder circuits using standard CMOS gates technologies

Design and Implementation 4-Bit Quaternary MVL Arithmetic and Logic Unit

In the recent years, there were major importance to Multiple Valued Logic (MVL), where the most common reasons for considering the implementation of MVL circuits better then binary valued circuits are that reducing wiring congestion as compared to binary circuits, using a single conductor to transmit three or more discrete voltage or current values allows for greater information content per wire and the circuit cost models would be more economical. Therefore, in this paper the MVL concepts have been used to design 4-bit quaternary MVL Arithmetic and Logic Unit, which is considered a basic unit of a MVL microprocessor. It is the "heart" of a microprocessor and we could say that everything else in the microprocessor is there to support the ALU. The proposed Arithmetic and Logic Unit will do the operations as Addition, Subtraction, Maximum, Minimum and Invert. Simulation Program with Integrated Circuit Emphasis (SPICE) tool in Cadence simulator used in simulation the proposed Arithmetic and Logic Unit. The simulation results tells that the design is more efficient compared with the binary ALU and the circuit will be less area and less number of transistors