310 research outputs found
Image compression and energy harvesting for energy constrained sensors
Title from PDF of title page, viewed on June 21, 2013Dissertation advisor: Walter D. Leon-SalasVitaIncludes bibliographic references (pages 176-[187])Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2013The advances in complementary metal-oxide-semiconductor (CMOS) technology
have led to the integration of all components of electronic system into a single integrated
circuit. Ultra-low power circuit techniques have reduced the power consumption of circuits.
Moreover, solar cells with improved efficiency can be integrated on chip to harvest
energy from sunlight. As a result of all the above, a new class of miniaturized electronic
systems known as self-powered system on a chip has emerged. There is an increasing research
interest in the area of self-powered devices which provide cost-effective solutions
especially when these devices are used in the areas that changing or replacing batteries is
too costly. Therefore, image compression and energy harvesting are studied in this dissertation.
The integration of energy harvesting, image compression, and an image sensor
on the same chip provides the energy source to charge a battery, reduces the data rate, and improves the performance of wireless image sensors. Integrated circuits of image compression,
solar energy harvesting, and image sensors are studied, designed, and analyzed
in this work. In this dissertation, a hybrid image sensor that can perform the tasks of sensing and
energy harvesting is presented. Photodiodes of hybrid image sensor can be programmed
as image sensors or energy harvesting cells. The hybrid image sensor can harvest energy
in between frames, in sleep mode, and even when it is taking images. When sensing
images and harvesting energy are both needed at the same time, some pixels have to
work as sensing pixels, and the others have to work as solar cells. Since some pixels are
devoted to harvest energy, the resolution of the image will be reduced. To preserve the
resolution or to keep the fair resolution when a lot of energy collection is needed, image
reconstruction algorithms and compressive sensing theory provide solutions to achieve
a good image quality. On the other hand, when the battery has enough charge, image
compression comes into the picture. Multiresolution decomposition image compression
provides a way to compress image data in order to reduce the energy need from data
transmission. The solution provided in this dissertation not only harvests energy but also
saves energy resulting long lasting wireless sensors. The problem was first studied at the system level to identify the best system-level
configuration which was then implemented on silicon. As a proof of concept, a 32 x 32 array of hybrid image sensor, a 32 x 32 array of image sensor with multiresolution decomposition compression, and a compressive sensing converter have been designed
and fabricated in a standard 0.5 [micrometer] CMOS process. Printed circuit broads also have been
designed to test and verify the proposed and fabricated chips. VHDL and Matlab codes
were written to generate the proper signals to control, and read out data from chips. Image
processing and recovery were carried out in Matlab. DC-DC converters were designed to
boost the inherently low voltage output of the photodiodes. The DC-DC converter has
also been improved to increase the efficiency of power transformation.Introduction -- Hybrid imager system and circuit design -- Hybrid imager energy harvesting and image acquisition results and discussion -- Detailed description and mathematical analysis for a circuit of energy harvesting using on-chip solar cells -- Multiresolution decomposition for lossless and near-lossless compression -- An incremental [sigma-delta] converter for compressive sensing -- Detailed description of a sigma-delta random demodulator converter architecture for compressive sensing applications -- Conclusion -- Appendix A. Chip pin-out -- Appendix B. Schematics -- Appendix C. Pictures of custom PC
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Fully-passive switched-capacitor techniques for high performance SAR ADC design
In recent years, SAR ADC becomes more and more popular in various low-power applications such as wireless sensors and low energy radios due to its circuit simplicity, high power efficiency, and scaling compatibility. However, its speed is limited by its successive approximation procedures and its power efficiency greatly reduces with the ADC resolution going beyond 10 bit. To address these issues, this thesis proposes to embed two techniques: 1) compressive sensing (CS) and 2) noise shaping (NS) to a conventional SAR ADC. The realization of both techniques are based on fully-passive switched-capacitor techniques.
CS is a recently emerging sampling paradigm, stating that the sparsity of a signal can be exploited to reduce the ADC sampling rate below the Nyquist rate. Different from conventional CS frameworks which require dedicated analog CS encoders, this thesis proposes a fully-passive CS-SAR ADC architecture which only requires minor modification to a conventional SAR ADC. Two chips are fabricated in a 0.13 µm process to prove the concept. One chip is a single-channel CS-SAR ADC which can reduce the ADC conversion rate by 4 times, thus reducing the ADC power by 4 times. In many wireless sensing applications, multiple ADCs are commonly required to sense multi-channel signals such as multi-lead ECG sensing and parallel neural recording. Therefore, the other chip is a multi-channel CS-SAR ADC which can simultaneously convert 4-channel signals with a sampling rate of one channel’s Nyquist rate. At 0.8 V and 1 MS/s, both chips achieve an effective Walden FoM of around 5 fJ/conversion-step.
This thesis also proposes a novel NS SAR ADC architecture that is simple, robust and low power for high-resolution applications. Compared to conventional ∆Σ ADCs, it replaces the power-hungry active integrator with a passive integrator which only requires one switch and two capacitors. Compared to previous 1st-order NS SAR ADC works, it achieves the best NS performance and can be easily extended to 2nd-order. A 1st-order 10-bit NS SAR ADC is fabricated in a 0.13 µm process. Through NS, SNDR increases by 6 dB with OSR doubled, achieving a 12- bit ENOB at OSR = 8. An improved version of a 2nd-order 9-bit NS SAR ADC is designed and simulated in a 40 nm process. The SNDR increases by 10 dB with OSR doubled, achieving a 14-bit ENOB at OSR = 16. At a bandwidth of 312.5 kHz, the Schreier FoM is 181 dB and the Walden FoM is 12.5 fJ/conversion-step, proving that the proposed NS SAR ADC architecture can achieve high resolution and high power efficiency simultaneously.Electrical and Computer Engineerin
A study of multilevel partial response signalling for transmission in a basic supergroup bandwidth
Includes bibliographical references.The work in this thesis is primarily directed toward the design, construction and testing of an experimental multilevel partial response signalling baseband system. The system will find practical application in existing frequency division multiplexed-frequency modulated microwave links. The basic supergroup bandwidth of these links is 240 kHz. The design requires a transmission rate of 1.024 Mb/s in this bandwidth. Class-4 15 partial response signalling is the coding technique suitable to achieve this. A pilot tone scheme is used to facilitate symbol timing recovery at the demodulator. A sixth order Butterworth low pass filter approximates the ideal raised-cosine Nyquist channel. A theoretical discussion on impairments caused by deviation from this channel is given. Since the experimental system was non-ideal, it produced a degradation in the channel signal to noise ratio. This degradation, coupled with other factors, showed that further development was necessary for the system to be suitable for connection into an existing microwave link
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