A fast engineering approach to high efficiency power amplifier linearization for avionics applications

This PhD thesis provides a fast engineering approach to the design of digital predistortion (DPD) linearizers from several perspectives: i) enhancing the off-line training performance of open-loop DPD, ii) providing robustness and reducing the computational complexity of the parameters identification subsystem and, iii) importing machine learning techniques to favor the automatic tuning of power amplifiers (PAs) and DPD linearizers with several free-parameters to maximize power efficiency while meeting the linearity specifications. One of the essential parts of unmanned aerial vehicles (UAV) is the avionics, being the radio control one of the earliest avionics present in the UAV. Unlike the control signal, for transferring user data (such as images, video, etc.) real-time from the drone to the ground station, large transmission rates are required. The PA is a key element in the transmitter chain to guarantee the data transmission (video, photo, etc.) over a long range from the ground station. The more linear output power, the better the coverage or alternatively, with the same coverage, better SNR allows the use of high-order modulation schemes and thus higher transmission rates are achieved. In the context of UAV wireless communications, the power consumption, size and weight of the payload is of significant importance. Therefore, the PA design has to take into account the compromise among bandwidth, output power, linearity and power efficiency (very critical in battery-supplied devices). The PA can be designed to maximize its power efficiency or its linearity, but not both. Therefore, a way to deal with this inherent trade-off is to design high efficient amplification topologies and let the PA linearizers take care of the linearity requirements. Among the linearizers, DPD linearization is the preferred solution to both academia and industry, for its high flexibility and linearization performance. In order to save as many computational and power resources as possible, the implementation of an open-loop DPD results a very attractive solution for UAV applications. This thesis contributes to the PA linearization, especially on off-line training for open-loop DPD, by presenting two different methods for reducing the design and operating costs of an open-loop DPD, based on the analysis of the DPD function. The first method focuses on the input domain analysis, proposing mesh-selecting (MeS) methods to accurately select the proper samples for a computationally efficient DPD parameter estimation. Focusing in the MeS method with better performance, the memory I-Q MeS method is combined with feature extraction dimensionality reduction technique to allow a computational complexity reduction in the identification subsystem by a factor of 65, in comparison to using the classical QR-LS solver and consecutive samples selection. In addition, the memory I-Q MeS method has been proved to be of crucial interest when training artificial neural networks (ANN) for DPD purposes, by significantly reducing the ANN training time. The second method involves the use of machine learning techniques in the DPD design procedure to enlarge the capacity of the DPD algorithm when considering a high number of free parameters to tune. On the one hand, the adaLIPO global optimization algorithm is used to find the best parameter configuration of a generalized memory polynomial behavioral model for DPD. On the other hand, a methodology to conduct a global optimization search is proposed to find the optimum values of a set of key circuit and system level parameters, that properly combined with DPD linearization and crest factor reduction techniques, can exploit at best dual-input PAs in terms of maximizing power efficiency along wide bandwidths while being compliant with the linearity specifications. The advantages of these proposed techniques have been validated through experimental tests and the obtained results are analyzed and discussed along this thesis.Aquesta tesi doctoral proporciona unes pautes per al disseny de linealitzadors basats en predistorsió digital (DPD) des de diverses perspectives: i) millorar el rendiment del DPD en llaç obert, ii) proporcionar robustesa i reduir la complexitat computacional del subsistema d'identificació de paràmetres i, iii) incorporació de tècniques d'aprenentatge automàtic per afavorir l'auto-ajustament d'amplificadors de potència (PAs) i linealitzadors DPD amb diversos graus de llibertat per poder maximitzar l’eficiència energètica i al mateix temps acomplir amb les especificacions de linealitat. Una de les parts essencials dels vehicles aeris no tripulats (UAV) _es l’aviònica, sent el radiocontrol un dels primers sistemes presents als UAV. Per transferir dades d'usuari (com ara imatges, vídeo, etc.) en temps real des del dron a l’estació terrestre, es requereixen taxes de transmissió grans. El PA _es un element clau de la cadena del transmissor per poder garantir la transmissió de dades a grans distàncies de l’estació terrestre. A major potència de sortida, més cobertura o, alternativament, amb la mateixa cobertura, millor relació senyal-soroll (SNR) la qual cosa permet l’ús d'esquemes de modulació d'ordres superiors i, per tant, aconseguir velocitats de transmissió més altes. En el context de les comunicacions sense fils en UAVs, el consum de potència, la mida i el pes de la càrrega útil són de vital importància. Per tant, el disseny del PA ha de tenir en compte el compromís entre ample de banda, potència de sortida, linealitat i eficiència energètica (molt crític en dispositius alimentats amb bateries). El PA es pot dissenyar per maximitzar la seva eficiència energètica o la seva linealitat, però no totes dues. Per tant, per afrontar aquest compromís s'utilitzen topologies amplificadores d'alta eficiència i es deixa que el linealitzador s'encarregui de garantir els nivells necessaris de linealitat. Entre els linealitzadors, la linealització DPD és la solució preferida tant per al món acadèmic com per a la indústria, per la seva alta flexibilitat i rendiment. Per tal d'estalviar tant recursos computacionals com consum de potència, la implementació d'un DPD en lla_c obert resulta una solució molt atractiva per a les aplicacions UAV. Aquesta tesi contribueix a la linealització del PA, especialment a l'entrenament fora de línia de linealitzadors DPD en llaç obert, presentant dos mètodes diferents per reduir el cost computacional i augmentar la fiabilitat dels DPDs en llaç obert. El primer mètode se centra en l’anàlisi de l’estadística del senyal d'entrada, proposant mètodes de selecció de malla (MeS) per seleccionar les mostres més significatives per a una estimació computacionalment eficient dels paràmetres del DPD. El mètode proposat IQ MeS amb memòria es pot combinar amb tècniques de reducció del model del DPD i d'aquesta manera poder aconseguir una reducció de la complexitat computacional en el subsistema d’identificació per un factor de 65, en comparació amb l’ús de l'algoritme clàssic QR-LS i selecció de mostres d'entrenament consecutives. El segon mètode consisteix en l’ús de tècniques d'aprenentatge automàtic pel disseny del DPD quan es considera un gran nombre de graus de llibertat (paràmetres) per sintonitzar. D'una banda, l'algorisme d’optimització global adaLIPO s'utilitza per trobar la millor configuració de paràmetres d'un model polinomial amb memòria generalitzat per a DPD. D'altra banda, es proposa una estratègia per l’optimització global d'un conjunt de paràmetres clau per al disseny a nivell de circuit i sistema, que combinats amb linealització DPD i les tècniques de reducció del factor de cresta, poden maximitzar l’eficiència de PAs d'entrada dual de gran ample de banda, alhora que compleixen les especificacions de linealitat. Els avantatges d'aquestes tècniques proposades s'han validat mitjançant proves experimentals i els resultats obtinguts s'analitzen i es discuteixen al llarg d'aquesta tesi

Digital Signal Processing Techniques Applied to Radio over Fiber Systems

The dissertation aims to analyze different Radio over Fiber systems for the front-haul applications. Particularly, analog radio over fiber (A-RoF) are simplest and suffer from nonlinearities, therefore, mitigating such nonlinearities through digital predistortion are studied. In particular for the long haul A-RoF links, direct digital predistortion technique (DPDT) is proposed which can be applied to reduce the impairments of A-RoF systems due to the combined effects of frequency chirp of the laser source and chromatic dispersion of the optical channel. Then, indirect learning architecture (ILA) based structures namely memory polynomial (MP), generalized memory polynomial (GMP) and decomposed vector rotation (DVR) models are employed to perform adaptive digital predistortion with low complexities. Distributed feedback (DFB) laser and vertical capacity surface emitting lasers (VCSELs) in combination with single mode/multi-mode fibers have been linearized with different quadrature amplitude modulation (QAM) formats for single and multichannel cases. Finally, a feedback adaptive DPD compensation is proposed. Then, there is still a possibility to exploit the other realizations of RoF namely digital radio over fiber (D-RoF) system where signal is digitized and transmits the digitized bit streams via digital optical communication links. The proposed solution is robust and immune to nonlinearities up-to 70 km of link length. Lastly, in light of disadvantages coming from A-RoF and D-RoF, it is still possible to take only the advantages from both methods and implement a more recent form knows as Sigma Delta Radio over Fiber (S-DRoF) system. Second Order Sigma Delta Modulator and Multi-stAge-noise-SHaping (MASH) based Sigma Delta Modulator are proposed. The workbench has been evaluated for 20 MHz LTE signal with 256 QAM modulation. Finally, The 6x2 GSa/s sigma delta modulators are realized on FPGA to show a real time demonstration of S-DRoF system. The demonstration shows that S-DRoF is a competitive competitor for 5G sub-6GHz band applications

Field Programmable Gate Arrays (FPGAs) II

This Edited Volume Field Programmable Gate Arrays (FPGAs) II is a collection of reviewed and relevant research chapters, offering a comprehensive overview of recent developments in the field of Computer and Information Science. The book comprises single chapters authored by various researchers and edited by an expert active in the Computer and Information Science research area. All chapters are complete in itself but united under a common research study topic. This publication aims at providing a thorough overview of the latest research efforts by international authors on Computer and Information Science, and open new possible research paths for further novel developments

Realization Limits of Impulse-Radio UWB Indoor Localization Systems

In this work, the realization limits of an impulse-based Ultra-Wideband (UWB) localization system for indoor applications have been thoroughly investigated and verified by measurements. The analysis spans from the position calculation algorithms, through hardware realization and modeling, up to the localization experiments conducted in realistic scenarios. The main focus was put on identification and characterization of limiting factors as well as developing methods to overcome them

Electronics for Sensors

The aim of this Special Issue is to explore new advanced solutions in electronic systems and interfaces to be employed in sensors, describing best practices, implementations, and applications. The selected papers in particular concern photomultiplier tubes (PMTs) and silicon photomultipliers (SiPMs) interfaces and applications, techniques for monitoring radiation levels, electronics for biomedical applications, design and applications of time-to-digital converters, interfaces for image sensors, and general-purpose theory and topologies for electronic interfaces

Linear Operation of Switch-Mode Outphasing Power Amplifiers

Radio transceivers are playing an increasingly important role in modern society. The ”connected” lifestyle has been enabled by modern wireless communications. The demand that has been placed on current wireless and cellular infrastructure requires increased spectral efficiency however this has come at the cost of power efficiency. This work investigates methods of improving wireless transceiver efficiency by enabling more efficient power amplifier architectures, specifically examining the role of switch-mode power amplifiers in macro cell scenarios. Our research focuses on the mechanisms within outphasing power amplifiers which prevent linear amplification. From the analysis it was clear that high power non-linear effects are correctable with currently available techniques however non-linear effects around the zero crossing point are not. As a result signal processing techniques for suppressing and avoiding non-linear operation in low power regions are explored. A novel method of digital pre-distortion is presented, and conventional techniques for linearisation are adapted for the particular needs of the outphasing power amplifier. More unconventional signal processing techniques are presented to aid linearisation of the outphasing power amplifier, both zero crossing and bandwidth expansion reduction methods are designed to avoid operation in nonlinear regions of the amplifiers. In combination with digital pre-distortion the techniques will improve linearisation efforts on outphasing systems with dynamic range and bandwidth constraints respectively. Our collaboration with NXP provided access to a digital outphasing power amplifier, enabling empirical analysis of non-linear behaviour and comparative analysis of behavioural modelling and linearisation efforts. The collaboration resulted in a bench mark for linear wideband operation of a digital outphasing power amplifier. The complimentary linearisation techniques, bandwidth expansion reduction and zero crossing reduction have been evaluated in both simulated and practical outphasing test benches. Initial results are promising and indicate that the benefits they provide are not limited to the outphasing amplifier architecture alone. Overall this thesis presents innovative analysis of the distortion mechanisms of the outphasing power amplifier, highlighting the sensitivity of the system to environmental effects. Practical and novel linearisation techniques are presented, with a focus on enabling wide band operation for modern communications standards

Dirty RF Signal Processing for Mitigation of Receiver Front-end Non-linearity

Moderne drahtlose Kommunikationssysteme stellen hohe und teilweise gegensätzliche Anforderungen an die Hardware der Funkmodule, wie z.B. niedriger Energieverbrauch, große Bandbreite und hohe Linearität. Die Gewährleistung einer ausreichenden Linearität ist, neben anderen analogen Parametern, eine Herausforderung im praktischen Design der Funkmodule. Der Fokus der Dissertation liegt auf breitbandigen HF-Frontends für Software-konfigurierbare Funkmodule, die seit einigen Jahren kommerziell verfügbar sind. Die praktischen Herausforderungen und Grenzen solcher flexiblen Funkmodule offenbaren sich vor allem im realen Experiment. Eines der Hauptprobleme ist die Sicherstellung einer ausreichenden analogen Performanz über einen weiten Frequenzbereich. Aus einer Vielzahl an analogen Störeffekten behandelt die Arbeit die Analyse und Minderung von Nichtlinearitäten in Empfängern mit direkt-umsetzender Architektur. Im Vordergrund stehen dabei Signalverarbeitungsstrategien zur Minderung nichtlinear verursachter Interferenz - ein Algorithmus, der besser unter "Dirty RF"-Techniken bekannt ist. Ein digitales Verfahren nach der Vorwärtskopplung wird durch intensive Simulationen, Messungen und Implementierung in realer Hardware verifiziert. Um die Lücken zwischen Theorie und praktischer Anwendbarkeit zu schließen und das Verfahren in reale Funkmodule zu integrieren, werden verschiedene Untersuchungen durchgeführt. Hierzu wird ein erweitertes Verhaltensmodell entwickelt, das die Struktur direkt-umsetzender Empfänger am besten nachbildet und damit alle Verzerrungen im HF- und Basisband erfasst. Darüber hinaus wird die Leistungsfähigkeit des Algorithmus unter realen Funkkanal-Bedingungen untersucht. Zusätzlich folgt die Vorstellung einer ressourceneffizienten Echtzeit-Implementierung des Verfahrens auf einem FPGA. Abschließend diskutiert die Arbeit verschiedene Anwendungsfelder, darunter spektrales Sensing, robuster GSM-Empfang und GSM-basiertes Passivradar. Es wird gezeigt, dass nichtlineare Verzerrungen erfolgreich in der digitalen Domäne gemindert werden können, wodurch die Bitfehlerrate gestörter modulierter Signale sinkt und der Anteil nichtlinear verursachter Interferenz minimiert wird. Schließlich kann durch das Verfahren die effektive Linearität des HF-Frontends stark erhöht werden. Damit wird der zuverlässige Betrieb eines einfachen Funkmoduls unter dem Einfluss der Empfängernichtlinearität möglich. Aufgrund des flexiblen Designs ist der Algorithmus für breitbandige Empfänger universal einsetzbar und ist nicht auf Software-konfigurierbare Funkmodule beschränkt.Today's wireless communication systems place high requirements on the radio's hardware that are largely mutually exclusive, such as low power consumption, wide bandwidth, and high linearity. Achieving a sufficient linearity, among other analogue characteristics, is a challenging issue in practical transceiver design. The focus of this thesis is on wideband receiver RF front-ends for software defined radio technology, which became commercially available in the recent years. Practical challenges and limitations are being revealed in real-world experiments with these radios. One of the main problems is to ensure a sufficient RF performance of the front-end over a wide bandwidth. The thesis covers the analysis and mitigation of receiver non-linearity of typical direct-conversion receiver architectures, among other RF impairments. The main focus is on DSP-based algorithms for mitigating non-linearly induced interference, an approach also known as "Dirty RF" signal processing techniques. The conceived digital feedforward mitigation algorithm is verified through extensive simulations, RF measurements, and implementation in real hardware. Various studies are carried out that bridge the gap between theory and practical applicability of this approach, especially with the aim of integrating that technique into real devices. To this end, an advanced baseband behavioural model is developed that matches to direct-conversion receiver architectures as close as possible, and thus considers all generated distortions at RF and baseband. In addition, the algorithm's performance is verified under challenging fading conditions. Moreover, the thesis presents a resource-efficient real-time implementation of the proposed solution on an FPGA. Finally, different use cases are covered in the thesis that includes spectrum monitoring or sensing, GSM downlink reception, and GSM-based passive radar. It is shown that non-linear distortions can be successfully mitigated at system level in the digital domain, thereby decreasing the bit error rate of distorted modulated signals and reducing the amount of non-linearly induced interference. Finally, the effective linearity of the front-end is increased substantially. Thus, the proper operation of a low-cost radio under presence of receiver non-linearity is possible. Due to the flexible design, the algorithm is generally applicable for wideband receivers and is not restricted to software defined radios

Analysis and design of low-power data converters

In a large number of applications the signal processing is done exploiting both analog and digital signal processing techniques. In the past digital and analog circuits were made on separate chip in order to limit the interference and other side effects, but the actual trend is to realize the whole elaboration chain on a single System on Chip (SoC). This choice is driven by different reasons such as the reduction of power consumption, less silicon area occupation on the chip and also reliability and repeatability. Commonly a large area in a SoC is occupied by digital circuits, then, usually a CMOS short-channel technological processes optimized to realize digital circuits is chosen to maximize the performance of the Digital Signal Proccessor (DSP). Opposite, the short-channel technology nodes do not represent the best choice for analog circuits. But in a large number of applications, the signals which are treated have analog nature (microphone, speaker, antenna, accelerometers, biopotential, etc.), then the input and output interfaces of the processing chip are analog/mixed-signal conversion circuits. Therefore in a single integrated circuit (IC) both digital and analog circuits can be found. This gives advantages in term of total size, cost and power consumption of the SoC. The specific characteristics of CMOS short-channel processes such as: • Low breakdown voltage (BV) gives a power supply limit (about 1.2 V). • High threshold voltage VTH (compared with the available voltage supply) fixed in order to limit the leakage power consumption in digital applications (of the order of 0.35 / 0.4V), puts a limit on the voltage dynamic, and creates many problems with the stacked topologies. • Threshold voltage dependent on the channel length VTH = f(L) (short channel effects). • Low value of the output resistance of the MOS (r0) and gm limited by speed saturation, both causes contribute to achieving a low intrinsic gain gmr0 = 20 to 26dB. • Mismatch which brings offset effects on analog circuits. make the design of high performance analog circuits very difficult. Realizing lowpower circuits is fundamental in different contexts, and for different reasons: lowering the power dissipation gives the capability to reduce the batteries size in mobile devices (laptops, smartphones, cameras, measuring instruments, etc.), increase the life of remote sensing devices, satellites, space probes, also allows the reduction of the size and weight of the heat sink. The reduction of power dissipation allows the realization of implantable biomedical devices that do not damage biological tissue. For this reason, the analysis and design of low power and high precision analog circuits is important in order to obtain high performance in technological processes that are not optimized for such applications. Different ways can be taken to reduce the effect of the problems related to the technology: • Circuital level: a circuit-level intervention is possible to solve a specific problem of the circuit (i.e. Techniques for bandwidth expansion, increase the gain, power reduction, etc.). • Digital calibration: it is the highest level to intervene, and generally going to correct the non-ideal structure through a digital processing, these aims are based on models of specific errors of the structure. • Definition of new paradigms. This work has focused the attention on a very useful mixed-signal circuit: the pipeline ADC. The pipeline ADCs are widely used for their energy efficiency in high-precision applications where a resolution of about 10-16 bits and sampling rates above hundreds of Mega-samples per second (telecommunication, radar, etc.) are needed. An introduction on the theory of pipeline ADC, its state of the art and the principal non-idealities that affect the energy efficiency and the accuracy of this kind of data converters are reported in Chapter 1. Special consideration is put on low-voltage low-power ADCs. In particular, for ADCs implemented in deep submicron technology nodes side effects called short channel effects exist opposed to older technology nodes where undesired effects are not present. An overview of the short channel effects and their consequences on design, and also power consuption reduction techniques, with particular emphasis on the specific techniques adopted in pipelined ADC are reported in Chapter 2. Moreover, another way may be undertaken to increase the accuracy and the efficiency of an ADC, this way is the digital calibration. In Chapter 3 an overview on digital calibration techniques, and furthermore a new calibration technique based on Volterra kernels are reported. In some specific applications, such as software defined radios or micropower sensor, some circuits should be reconfigurable to be suitable for different radio standard or process signals with different charateristics. One of this building blocks is the ADC that should be able to reconfigure the resolution and conversion frequency. A reconfigurable voltage-scalable ADC pipeline capable to adapt its voltage supply starting from the required conversion frequency was developed, and the results are reported in Chapter 4. In Chapter 5, a pipeline ADC based on a novel paradigm for the feedback loop and its theory is described