185 research outputs found

    COGNITIVE RADIO SOLUTION FOR IEEE 802.22

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    Current wireless systems suffer severe radio spectrum underutilization due to a number of problematic issues, including wasteful static spectrum allocations; fixed radio functionalities and architectures; and limited cooperation between network nodes. A significant number of research efforts aim to find alternative solutions to improve spectrum utilization. Cognitive radio based on software radio technology is one such novel approach, and the impending IEEE 802.22 air interface standard is the first based on such an approach. This standard aims to provide wireless services in wireless regional area network using TV spectrum white spaces. The cognitive radio devices employed feature two fundamental capabilities, namely supporting multiple modulations and data-rates based on wireless channel conditions and sensing a wireless spectrum. Spectrum sensing is a critical functionality with high computational complexity. Although the standard does not specify a spectrum sensing method, the sensing operation has inherent timing and accuracy constraints.This work proposes a framework for developing a cognitive radio system based on a small form factor software radio platform with limited memory resources and processing capabilities. The cognitive radio systems feature adaptive behavior based on wireless channel conditions and are compliant with the IEEE 802.22 sensing constraints. The resource limitations on implementation platforms post a variety of challenges to transceiver configurability and spectrum sensing. Overcoming these fundamental features on small form factors paves the way for portable cognitive radio devices and extends the range of cognitive radio applications.Several techniques are proposed to overcome resource limitation on a small form factor software radio platform based on a hybrid processing architecture comprised of a digital signal processor and a field programmable gate array. Hardware reuse and task partitioning over a number of processing devices are among the techniques used to realize a configurable radio transceiver that supports several communication modes, including modulations and data rates. In particular, these techniques are applied to build configurable modulation architecture and a configurable synchronization. A mode-switching architecture based on circular buffers is proposed to facilitate a reliable transitioning between different communication modes.The feasibility of efficient spectrum sensing based on a compressive sampling technique called "Fast Fourier Sampling" is examined. The configuration parameters are analyzed mathematically, and performance is evaluated using computer simulations for local spectrum sensing applications. The work proposed herein features a cooperative Fast Fourier sampling scheme to extend the narrowband and wideband sensing performance of this compressive sensing technique.The précis of this dissertation establishes the foundation of efficient cognitive radio implementation on small form factor software radio of hybrid processing architecture

    A low cost alternative to high performance PCM bit synchronizers

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    The Code Converter/Clock Regenerator (CCCR) provides a low-cost alternative to high-performance Pulse Code Modulation (PCM) bit synchronizers in environments with a large Signal-to-Noise Ratio (SNR). In many applications, the CCCR can be used in place of PCM bit synchronizers at about one fifth the cost. The CCCR operates at rates from 10 bps to 2.5 Mbps and performs PCM code conversion and clock regeneration. The CCCR has been integrated into a stand-alone system configurable from one to six channels and has also been designed for use in VMEbus compatible systems

    RapidRadio: A Domain-Specific Productivity Enhancing Framework

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    The RapidRadio framework for signal classification and receiver deployment is discussed. The framework is a productivity enhancing tool that reduces the required knowledge-base for implementing a receiver on an FPGA-based SDR platform. The ultimate objective of this framework is to identify unknown signals and to build FPGA-based receivers capable of receiving them. The architecture of the receiver deployed by the framework and its implementation are discussed. The framework's capacity to classify a signal and deploy a functional receiver is validated with over-the-air experiments

    Simulación de una cadena de comunicaciones DS-CDMA - Simulació d’una cadena de comunicacions DS-CDMA

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    Català: En aquest projecte s'ha analitzat e implementat un sistema basat amb DSSS-CDMA amb un receptor comú y diversos transmissors sobre una plataforma modular en Matlab, essent aquesta una eina de validació teòrica. S'ha primat aquesta per sobre d'una implementació en DSP principalment pel cost ecònomic de les plaques DSP. Així, s'ha decidit fer una implementació en Matlab amb les restriccions pròpies d'una placa DSP. El principal objectiu del projecte es la validació del sistema mitjançant la simulació a nivell de mostra sense restriccions de memòria. El proper pas seria la implementació en plaques DSP, peró això s'escapa del objectiu d'aquest projecte. És per això que s'ha dissenyat un sistema que pugi processar les dades amb pocs recursos mitjançant Matlab, tots marcats per una serie de variables. El transmissor es composa de diversos mòduls invariants que son el codificador, modulador, spreader, zero padder, pols conformador i el up converter que estan encadenats per generar la senyal a transmetre per cada un dels diversos usuaris. Totes aquestes senyals passen per un canal d'esvaniment lent amb soroll Gaussià blanc que modelitza un medi de comunicacions mòbil. Finalment el receptor rep totes les senyals y les processa en una serie de mòduls independents formats per un filtre pas baix, downconverter, filtre adaptat, sincronitzador, downsampler, equalitzador, despreader, demodulador y decodificador. En aquest treball es pot observar en la secció de Resultats les captures de la senyal a cada una de les diverses fases seguides d'una breu explicació. Finalment es tracten les conclusions i les properes vies d'investigació.Castellano: En este proyecto se ha analizado e implementado un sistema basado en DSSS-CDMA con un receptor común y varios transmisores sobre una plataforma modular en Matlab, siendo ésta una herramienta de validación teórica. Se ha primado esta sobre una implementación en DSP por el coste económico de las placas DSP. Así que se ha decidido hacer una implementación en Matlab con las constricciones propias de una placa DSP. El objetivo principal del proyecto es la validación del sistema mediante la simulación a nivel de muestra sin restricciones de memoria. El siguiente paso sería la implementación en placas DSP pero esto se escapa del objetivo de este proyecto. Para ello se ha diseñado un sistema que pueda procesar los datos con pocos recursos en Matlab, marcados por una serie de variables. El transmisor se compone de varios módulos invariantes que son el codificador, modulador, spreader, zero padder, pulse shaper y el up converter que encadenados generan la señal a transmitir de cada uno de los distintos usuarios. Todas estas señales pasan por un canal con desvanecimientos lentos y ruido aditivo gaussiano que modeliza un medio de comunicaciones móvil. Finalmente el receptor recibe todas las señales y las procesa en una serie de módulos independientes formados por un filtro paso bajo, downconverter, filtro adaptado, sincronizador, downsampler, equalizador, despreader, demodulador y decodificador. En este trabajo se puede observar en la sección Resultados las capturas de la señal en cada una de las distintas fases seguida de una breve explicación. Para finalmente llegar a la sección de Conclusiones y Futuras líneas de investigación.English: This project has analyzed and implemented a system based on DS-CDMA with a common receiver and multiple transmitters on a modular platform in Matlab, which is used for theoretical validation tool. This platform has been chosen over a DSP implementation due to the economic cost of DSP boards. So, it was decided to implement it using Matlab considering the inherent constraints in a DSP board. Project's main objective is to validate this system by having a simulation at a sample level which has no memory constraints. The next step would be to implement this in DSP boards; however this is beyond the scope of this project. A system has been designed that can process data with few resources in Matlab environment. The system developed is highly configurable using some input parameters. The transmitter consists of several modules that are invariant which are encoder, modulator, spreader, zero padder, pulse shaper and converter. These chained modules generate each user transmitted signal. Once these transmittersâ signals have been generated, they pass through a slowly fading channel with additive Gaussian noise which models a means of mobile communications. Ultimately the receiver gets all signals and processes them in a series of independent modules consisting of a low pass filter, downconverter, matched filter, synchronizer, downsampler, equalizer, despreader, demodulator and decoder. This work can be seen in the â Resultsâ section where there are screens of the signal in each of the phases followed by a brief justification

    Configurable pseudo noise radar imaging system enabling synchronous MIMO channel extension

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    In this article, we propose an evolved system design approach to ultra-wideband (UWB) radar based on pseudo-random noise (PRN) sequences, the key features of which are its user-adaptability to meet the demands provided by desired microwave imaging applications and its multichannel scalability. In light of providing a fully synchronized multichannel radar imaging system for short-range imaging as mine detection, non-destructive testing (NDT) or medical imaging, the advanced system architecture is presented with a special focus put on the implemented synchronization mechanism and clocking scheme. The core of the targeted adaptivity is provided by means of hardware, such as variable clock generators and dividers as well as programmable PRN generators. In addition to adaptive hardware, the customization of signal processing is feasible within an extensive open-source framework using the Red Pitaya ® data acquisition platform. A system benchmark in terms of signal-to-noise ratio (SNR), jitter, and synchronization stability is conducted to determine the achievable performance of the prototype system put into practice. Furthermore, an outlook on the planned future development and performance improvement is provided

    Self-configurable radio receiver system and method for use with signals without prior knowledge of signal defining characteristics

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    A method, radio receiver, and system to autonomously receive and decode a plurality of signals having a variety of signal types without a priori knowledge of the defining characteristics of the signals is disclosed. The radio receiver is capable of receiving a signal of an unknown signal type and, by estimating one or more defining characteristics of the signal, determine the type of signal. The estimated defining characteristic(s) is/are utilized to enable the receiver to determine other defining characteristics. This in turn, enables the receiver, through multiple iterations, to make a maximum-likelihood (ML) estimate for each of the defining characteristics. After the type of signal is determined by its defining characteristics, the receiver selects an appropriate decoder from a plurality of decoders to decode the signal

    Onboard multichannel demultiplexer/demodulator

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    An investigation performed for NASA LeRC by COMSAT Labs, of a digitally implemented on-board demultiplexer/demodulator able to process a mix of uplink carriers of differing bandwidths and center frequencies and programmable in orbit to accommodate variations in traffic flow is reported. The processor accepts high speed samples of the signal carried in a wideband satellite transponder channel, processes these as a composite to determine the signal spectrum, filters the result into individual channels that carry modulated carriers and demodulate these to recover their digital baseband content. The processor is implemented by using forward and inverse pipeline Fast Fourier Transformation techniques. The recovered carriers are then demodulated using a single digitally implemented demodulator that processes all of the modulated carriers. The effort has determined the feasibility of the concept with multiple TDMA carriers, identified critical path technologies, and assessed the potential of developing these technologies to a level capable of supporting a practical, cost effective on-board implementation. The result is a flexible, high speed, digitally implemented Fast Fourier Transform (FFT) bulk demultiplexer/demodulator

    Combined Matched Filter and Arbitrary Interpolator for Symbol Timing Synchronization in SDR Receivers

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    Sincronização de quadro e frequência para OFDM no padrão IEEE 802.15.4g : algoritmos e implementação em hardware

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    Orientadores: Renato da Rocha Lopes, Eduardo Rodrigues de LimaDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: O objetivo deste trabalho é propor métodos de sincronização de quadro e de frequência de portadora para a camada física MR-OFDM do padrão IEEE 802.15.4g, começando pela pesquisa de algoritmos, passando pelas etapas de modelagem e simulação em alto nível, e finalmente implementando e avaliando os métodos propostos em hardware. A sincronização de quadro é o processo responsável por detectar o início do dado transmitido, ou seja, a primeira amostra válida do sinal de interesse. No caso de sistemas OFDM, onde o sinal transmitido é composto por um ou mais símbolos OFDM (cada símbolo sendo composto por uma quantidade fixa de amostras), o objetivo é detectar a borda ou janelamento de tais símbolos OFDM, ou seja, onde começa e termina cada um deles. A sincronização de frequência, por sua vez, consiste em estimar e compensar o erro de frequência de portadora, causado principalmente pelo descasamento dos osciladores do transmissor e do receptor. Com base em estudos preliminares, selecionamos o algoritmo de Minn para a detecção de quadro. Para a correção de erro de frequência, dividimos o processo em duas etapas, como é geralmente proposto na literatura: primeiro, o erro de frequência fracionário é estimado no domínio do tempo durante a detecção de quadro e compensado via rotação de sinal; após a conversão do domínio do tempo para o domínio da frequência, o erro de frequência inteiro é estimado e compensado utilizando um novo e simples algoritmo que será proposto e detalhado neste trabalho. Os algoritmos propostos foram implementados em hardware e uma plataforma de verificação baseada em FPGA foi criada para avaliar o seu desempenho. Os módulos implementados são parte de um projeto que está sendo desenvolvido no Instituto de Pesquisa Eldorado (Campinas) que tem como objetivo implementar em ASIC um transceptor compatível com o padrão IEEE 802.15.4gAbstract: The objective of this work is proposing methods of frame and frequency synchronization for the MR-OFDM PHY of IEEE 802.15.4g standard, starting with the research of state-of-the-art algorithms, passing through modeling, high-level simulations, and finally implementing and evaluating the proposed methods in hardware. Frame synchronization is the process responsible for detecting the beginning of transmitted data and, in the case of OFDM systems, the border of each OFDM symbol, while frequency synchronization consists of estimating and compensating the Carrier Frequency Offset (CFO) caused mainly by a mismatch between the transmitter and receiver oscillators. Based on the initial studies, we selected Minn¿s algorithm for frame detection. For the CFO correction, we split the process into two steps, as commonly proposed in the literature: first, the Fractional CFO is estimated in the time domain during the frame detection and compensated via signal rotation; after the conversion from time to frequency domain, the Integer CFO is estimated and compensated with a novel and simple algorithm that will be detailed in this work. The proposed algorithms were implemented in hardware and inserted in an FPGA-based verification platform for performance measurement. The implemented modules are part of a project that is under development at Eldorado Research Institute (Campinas) and aims to implement in ASIC a transceiver compliant to the IEEE 802.15.4g standardMestradoTelecomunicações e TelemáticaMestra em Engenharia Elétric

    Architecture Design of Frequency Domain Processing for Flexible and Re-configurable WiMAX OFDMA Receiver

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    AbstractThis paper proposes hardware architecture of WiMAX OFDMA frequency domain processing system. The system mainly consists of channel estimator, equalizer, and subcarrier de-allocator. The system is optimized for flexible and re-configurable WiMAX OFDMA receiver. The flexibility feature is obtained by employing flexible control unit approach using task FIFO. Using this scheme, the designed system can handle various and complex data structure within OFDMA frame. The propesed architecture has been implemented in 0.13μm CMOS technology. The implementation result shows that chip area is about 0.45 mm2 and able to work in targeted system clock 54MHz
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