An Intelligent Auxiliary Vacuum Brake System

The purpose of this paper focuses on designing an intelligent, compact, reliable, and robust auxiliary vacuum brake system (VBS) with Kalman filter and self-diagnosis scheme. All of the circuit elements in the designed system are integrated into one programmable system-on-chip (PSoC) with entire computational algorithms implemented by software. In this system, three main goals are achieved: (a) Kalman filter and hysteresis controller algorithms are employed within PSoC chip by software to surpass the noises and disturbances from hostile surrounding in a vehicle. (b) Self-diagnosis scheme is employed to identify any breakdown element of the auxiliary vacuum brake system. (c) Power MOSFET is utilized to implement PWM pump control and compared with relay control. More accurate vacuum pressure control has been accomplished as well as power energy saving. In the end, a prototype has been built and tested to confirm all of the performances claimed above

A programmable microsystem using system-on-chip for real-time biotelemetry

A telemetry microsystem, including multiple sensors, integrated instrumentation and a wireless interface has been implemented. We have employed a methodology akin to that for System-on-Chip microelectronics to design an integrated circuit instrument containing several "intellectual property" blocks that will enable convenient reuse of modules in future projects. The present system was optimized for low-power and included mixed-signal sensor circuits, a programmable digital system, a feedback clock control loop and RF circuits integrated on a 5 mm × 5 mm silicon chip using a 0.6 μm, 3.3 V CMOS process. Undesirable signal coupling between circuit components has been investigated and current injection into sensitive instrumentation nodes was minimized by careful floor-planning. The chip, the sensors, a magnetic induction-based transmitter and two silver oxide cells were packaged into a 36 mm × 12 mm capsule format. A base station was built in order to retrieve the data from the microsystem in real-time. The base station was designed to be adaptive and timing tolerant since the microsystem design was simplified to reduce power consumption and size. The telemetry system was found to have a packet error rate of 10<sup>-</sup><sup>3</sup> using an asynchronous simplex link. Trials in animal carcasses were carried out to show that the transmitter was as effective as a conventional RF device whilst consuming less power

Universal Evaluation Platform

Universal Evaluation Platform (UEP), the lab bench on a board, seeks to streamline the process of testing new integrated circuit products. It replaces costly custom test fixtures, and allows test engineers to fully characterize new devices before datasheets exist. Features include fixed and adjustable voltage supplies, common digital communication protocols, filter generation via digital signal processing, and a user interface. Communication and digital signal processing were implemented on an FPGA, while power supplies were assembled through custom circuitry. The platform aims to save engineering time and resources, while accommodating testing of a wide array of products

Memory and information processing in neuromorphic systems

A striking difference between brain-inspired neuromorphic processors and current von Neumann processors architectures is the way in which memory and processing is organized. As Information and Communication Technologies continue to address the need for increased computational power through the increase of cores within a digital processor, neuromorphic engineers and scientists can complement this need by building processor architectures where memory is distributed with the processing. In this paper we present a survey of brain-inspired processor architectures that support models of cortical networks and deep neural networks. These architectures range from serial clocked implementations of multi-neuron systems to massively parallel asynchronous ones and from purely digital systems to mixed analog/digital systems which implement more biological-like models of neurons and synapses together with a suite of adaptation and learning mechanisms analogous to the ones found in biological nervous systems. We describe the advantages of the different approaches being pursued and present the challenges that need to be addressed for building artificial neural processing systems that can display the richness of behaviors seen in biological systems.Comment: Submitted to Proceedings of IEEE, review of recently proposed neuromorphic computing platforms and system

Can my chip behave like my brain?

Many decades ago, Carver Mead established the foundations of neuromorphic systems. Neuromorphic systems are analog circuits that emulate biology. These circuits utilize subthreshold dynamics of CMOS transistors to mimic the behavior of neurons. The objective is to not only simulate the human brain, but also to build useful applications using these bio-inspired circuits for ultra low power speech processing, image processing, and robotics. This can be achieved using reconfigurable hardware, like field programmable analog arrays (FPAAs), which enable configuring different applications on a cross platform system. As digital systems saturate in terms of power efficiency, this alternate approach has the potential to improve computational efficiency by approximately eight orders of magnitude. These systems, which include analog, digital, and neuromorphic elements combine to result in a very powerful reconfigurable processing machine.Ph.D

A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)

Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multi-core neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.Comment: 17 pages, 14 figure

Analog Reconfigurable Circuits

The aim of this paper is to present an overview of a new branch of analog electronics represented by analog reconfigurable circuits. The reconfiguration of analog circuits has been known and used since the beginnings of electronics, but the universal reconfigurable circuits called Field Programmable Analog Arrays (FPAA) have been developed over the last two decades. This paper presents the classification of analog circuit reconfiguration, examples of FPAA solutions obtained as academic projects and commercially available ones, as well as some application examples of the dynamic reconfiguration of FPAA.

Embedded System development with PSOC : orientation sensing and visualization with PSOC

This thesis describes a new embedded system development process. The thesis aims to demonstrate how embedded systems could be developed efficiently with the help of the new technological advances such as programmable systems on chips. A special focus is given on HW and SW programming of such systems. The project makes use of a new generation of a chip called Programmable System on Chip (PSoC) as its hardware platform. What distinguishes PSoC from a line of processors and system on chips is its programmable hardware. This feature allows embedded system designers to be able to customize part of the hardware programmatically in addition to writing a software application that runs on top of the system. This thesis introduces the development of an embedded system based on the PSoc chip and development environment provided by Cypress semiconductors. Finally, this thesis presents a position sensing application which demonstrates the development process of a modern day typical embedded system