255 research outputs found

    Delay models and design guidelines for MCML gates with resistor or PMOS load

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    In this paper we present propagation delay models for MCML gates with resistor- or triode-PMOS-based output I–V conversion. The dependence of the parasitic capacitance of triode PMOS devices is accurately evaluated for the first time in the literature. The proposed models are able to accurately predict the propagation delay as a function of the bias current ISS in different design scenarios which require different tradeoffs between speed, area and power efficiency. The proposed models are validated against transistor level simulations referring to a 28 ​nm CMOS process showing a maximum percentage error lower than 6.5%. Based on these models, a comparative analysis is carried out and useful guidelines for the design of MCML gates are proposed

    A study of Radiation-Tolerant Voltage-Controlled Oscillators designs in 65 nm bulk and 28 nm FDSOI CMOS technologies

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    Phase-locked loop (PLL) systems are widely employed in integrated circuits for space analog devices and communications systems that operate in radiation environments, where significant perturbations, especially in terms of phase noise, can be generated due to radiation particles. Among all the blocks that form a PLL system, previous research suggests the voltage-controlled oscillator (VCO) is one of the most critical components in terms of radiation tolerance and electric performance. Ring oscillators (ROs) and LC-tank VCOs have been commonly employed in high-performance PLLs. Nevertheless, both structures have drawbacks including a limited tuning range, high sensitivity to phase noise, limited radiation tolerance, and large design areas. In order to fulfill these high-performance requirements, a current-model logic (CML) based RO-VCO is presented as a possible solution capable of reducing the limitations of the commonly used structures and exploiting their advantages. The proposed hybrid VCO model includes passive components in its design which are the key parameters that define oscillation frequency of this structure. This tunable oscillator has been designed and tested in 65nm Bulk and 28 nm Fully depleted silicon-on-insulator (FDSOI) CMOS technologies The 65nm testchip was designed to compare the behavior of the proposed CML VCO with a current-starved RO and a radiation hardened by design (RHBD) LC-tank VCO in terms of tuning range, phase noise, Single event effect (SEE) sensitivity and design area. Simulations were carried out by applying a double exponential current pulse into different sensitive nodes of the three VCOs. In addition, SEE tests were conducted using pulsed laser experiments. Simulation and test results show that a CML VCO can effectively overcome the limitations presented by a RO-VCO and LC-tank VCO, achieving a wide range of tuning, and low sensitivity to noise and SEEs without the need for a large cross-section. Further studies of the proposed CML VCO were done on 28nm FDSOI in order to reduce the leakage current and increase the switching speed. the same current-starved VCO and CML VCO were implemented on this testchip, and simulations were performed by injecting a double exponential current pulse energy into the previously defined sensitive nodes. The results show SEE sensitivity improvement without narrowing the tuning range or affecting the phase noise response

    Transmetteurs photoniques sur silicium pour les transmissions optiques à grande capacité

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    Les applications exigeant des très nombreuses données (médias sociaux, diffusion vidéo en continu, mégadonnées, etc.) se développent à un rythme rapide, ce qui nécessite de plus en plus de liaisons optiques ultra-rapides. Ceci implique le développment des transmetteurs optiques intégrés et à bas coût et plus particulirement en photonique sur silicium en raison de ses avantages par rapport aux autres technologies (LiNbO3 et InP), tel que la compatibilité avec le procédé de fabrication CMOS. Les modulateurs optoélectronique sont un élément essentiel dans la communication op-tique. Beaucoup de travaux de recherche sont consacrées au développement de dispositifs optiques haut débit efficaces. Cependant, la conception de modulateurs en photonique sur sili-cium (SiP) haut débit est diffcile, principalement en raison de l'absence d'effet électro-optique intrinsèque dans le silicium. De nouvelles approches et de architectures plus performances doivent être développées afin de satisfaire aux critères réliés au système d'une liaison optique aux paramètres de conception au niveau du dispositif integré. En outre, la co-conception de circuits integrés photoniques sur silicium et CMOS est cruciale pour atteindre tout le potentiel de la technologie de photonique sur silicium. Ainsi cette thèse aborde les défits susmentionnés. Dans notre première contribution, nous préesentons pour la première fois un émetteur phononique sur silicium PAM-4 sans utiliser un convertisseur numérique analog (DAC)qui comprend un modulateur Mach Zehnder à électrodes segmentées SiP (LES-MZM) implémenté dans un procédé photonique sur silicium générique avec jonction PN latérale et son conducteur CMOS intégré. Des débits allant jusqu'à 38 Gb/s/chnnel sont obtenus sans utili-ser un convertisseur numérique-analogique externe. Nous présentons également une nouvelle procédure de génération de délai dans le excitateur de MOS complémentaire. Un effet, un délai robuste aussi petit que 7 ps est généré entre les canaux de conduite. Dans notre deuxième contribution, nous présentons pour la première fois un nouveau fac-teur de mérite (FDM) pour les modulateurs SiP qui inclut non seulement la perte optique et l'efficacité (comme les FDMs précédents), mais aussi la bande passante électro-optique du modulateur SiP (BWEO). Ce nouveau FDM peut faire correspondre les paramètres de conception physique du modulateur SiP à ses critères de performance au niveau du système, facilitant à la fois la conception du dispositif optique et l'optimisation du système. Pour la première fois nous définissons et utilisons la pénalité de puissance du modulateur (MPP) induite par le modulateur SiP pour étudier la dégradation des performances au niveau du système induite par le modulateur SiP dans une communication à base de modulation d'amplitude d'impulsion optique. Nous avons développé l'équation pour MPP qui inclut les facteurs de limitation du modulateur (perte optique, taux d'extinction limité et limitation de la bande passante électro-optique). Enfin, dans notre troisième contribution, une nouvelle méthodologie de conception pour les modulateurs en SiP intégré à haute débit est présentée. La nouvelle approche est basée sur la minimisation de la MPP SiP en optimisant l'architecture du modulateur et le point de fonctionnement. Pour ce processus, une conception en longueur unitaire du modulateur Mach Zehnder (MZM) peut être optimisée en suivant les spécifications du procédé de fabrication et les règles de conception. Cependant, la longueur et la tension de biais du d'éphaseur doivent être optimisées ensemble (par exemple selon vitesse de transmission et format de modulation). Pour vérifier l'approche d'optimisation proposée expérimentale mont, a conçu un modulateur photonique sur silicium en phase / quadrature de phase (IQ) ciblant le format de modulation 16-QAM à 60 Gigabaud. Les résultats expérimentaux prouvent la fiabilité de la méthodologie proposée. D'ailleurs, nous avons augmenté la vitesse de transmission jusqu'à 70 Gigabaud pour tester la limite de débit au système. Une transmission de données dos à dos avec des débits binaires de plus de 233 Gigabit/s/channel est observée. Cette méthodologie de conception ouvre ainsi la voie à la conception de la prochaine génération d'émetteurs intégrés à double polarisation 400+ Gigabit/s/channel.Data-hungry applications (social media, video streaming, big data, etc.) are expanding at a fast pace, growing demand for ultra-fast optical links. This driving force reveals need for low-cost, integrated optical transmitters and pushes research in silicon photonics because of its advantages over other platforms (i.e. LiNbO3 and InP), such as compatibility with CMOS fabrication processes, the ability of on-chip polarization manipulation, and cost effciency. Electro-optic modulators are an essential component of optical communication links and immense research is dedicated to developing effcient high-bitrate devices. However, the design of high-capacity Silicon Photonics (SiP) transmitters is challenging, mainly due to lack of inherent electro-optic effect in silicon. New design methodologies and performance merits have to be developed in order to map the system-level criteria of an optical link to the design parameters in device-level. In addition, co-design of silicon photonics and CMOS integrated circuits is crucial to reveal the full potential of silicon photonics. This thesis addresses the aforementioned challenges. In our frst contribution, for the frst time we present a DAC-less PAM-4 silicon photonic transmitter that includes a SiP lumped-element segmented-electrode Mach Zehnder modula-tor (LES-MZM) implemented in a generic silicon photonic process with lateral p-n junction and its co-designed CMOS driver. Using post processing, bitrates up to 38 Gb/s/channel are achieved without using an external digital to analog converter. We also presents a novel delay generation procedure in the CMOS driver. A robust delay as small as 7 ps is generated between the driving channels. In our second contribution, for the frst time we present a new figure of merit (FOM) for SiP modulators that includes not only the optical loss and effciency (like the prior FOMs), but also the SiP modulator electro-optic bandwidth ( BWEO). This new FOM can map SiP modulator physical design parameters to its system-level performance criteria, facilitating both device design and system optimization. For the frst time we define and employ the modulator power penalty (MPP) induced by the SiP modulator to study the system level performance degradation induced by SiP modulator in an optical pulse amplitude modulation link. We develope a closed-form equation for MPP that includes the SiP modulator limiting factors (optical loss, limited extinction ratio and electro-optic bandwidth limitation). Finally in our third contribution, we present a novel design methodology for integrated high capacity SiP modulators. The new approach is based on minimizing the power penalty of a SiP modulator (MPP) by optimizing modulator design and bias point. For the given process, a unit-length design of Mach Zehnder modulator (MZM) can be optimized following the process specifications and design rules. However, the length and the bias voltage of the phase shifter must be optimized together in a system context (e.g., baud rate and modulation format). Moreover, to verify the proposed optimization approach in experiment, we design an in-phase/quadrature-phase (IQ) silicon photonic modulator targeting 16-QAM modulation format at 60 Gbaud. Experimental results proves the reliability of our proposed methodology. We further push the baud rate up to 70 Gbaud to examine the capacity boundary of the device. Back to back data transmission with bitrates more than 233 Gb/s/channel are captured. This design methodology paves the way for designing the next generation of integrated dual- polarization 400+ Gb/s/channel transmitters

    A GHz-range, High-resolution Multi-modulus Prescaler for Extreme Environment Applications

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    The generation of a precise, low-noise, reliable clock source is critical to developing mixed-signal and digital electronic systems. The applications of such a clock source are greatly expanded if the clock source can be configured to output different clock frequencies. The phase-locked loop (PLL) is a well-documented architecture for realizing this configurable clock source. Principle to the configurability of a PLL is a multi-modulus divider. The resolution of this divider (or prescaler) dictates the resolution of the configurable PLL output frequency. In integrated PLL designs, such a multi-modulus prescaler is usually sourced from a GHz-range voltage-controlled oscillator. Therefore, a fully-integrated PLL ASIC requires the development of a high-speed, high-resolution multi-modulus prescaler. The design challenges associated with developing such a prescaler are compounded when the application requires the device to operate in an extreme environment. In these extreme environments (often extra-terrestrial), wide temperature ranges and radiation effects can adversely affect the operation of electronic systems. Even more problematic is that extreme temperatures and ionizing radiation can cause permanent damage to electronic devices. Typical commercial-off-the-shelf (COTS) components are not able withstand such an environment, and any electronics operating in these extreme conditions must be designed to accommodate such operation. This dissertation describes the development of a high-speed, high-resolution, multi-modulus prescaler capable of operating in an extreme environment. This prescaler has been developed using current-mode logic (CML) on a 180-nm silicon-germanium (SiGe) BiCMOS process. The prescaler is capable of operating up to at least 5.4 GHz over a division range of 16-48 with a total of 27 configurable moduli. The prescaler is designed to provide excellent ionizing radiation hardness, single-event latch-up (SEL) immunity, and single-event upset (SEU) resistance over a temperature range of −180°C to 125°C

    A Comprehensive Design Approach for a MZM Based PAM-4 Silicon Photonic Transmitter

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    A 4-level pulse amplitude modulation (PAM-4) silicon photonic transmitter targeting operation at 25 Gb/s is designed using an electrical-photonic co-design methodology. The prototype consists of an electrical circuit and a photonics circuit, which were designed in 130 nm IBM SiGe BiCMOS process and 130nm IME SOI CMOS process, respectively. Then the two parts will be interfaced via side-by-side wire bonding. The electrical die mainly includes a 12.5 GHz PLL, a full-rate 4- channel uncorrelated 27 − 1 pseudo-random binary sequence (PRBS) generator and CML drivers. The photonics die is a 2-segment Mach-Zehnder modulator (MZM) silicon photonics device with thermal tuning feature for PAM-4. Verilog-A model for the MZM entails the system simulation for optical devices together with electrical circuitry using custom IC design tools. A full-rate 4-channel uncorrelated PRBS design using transition matrix method is detailed, in which any two of the 4-channels can be used for providing random binary sequence to drive the two segments of the MZM to generate the PAM-4 signal

    Integrated Circuit Design for Hybrid Optoelectronic Interconnects

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    This dissertation focuses on high-speed circuit design for the integration of hybrid optoelectronic interconnects. It bridges the gap between electronic circuit design and optical device design by seamlessly incorporating the compact Verilog-A model for optical components into the SPICE-like simulation environment, such as the Cadence design tool. Optical components fabricated in the IME 130nm SOI CMOS process are characterized. Corresponding compact Verilog-A models for Mach-Zehnder modulator (MZM) device are developed. With this approach, electro-optical co-design and hybrid simulation are made possible. The developed optical models are used for analyzing the system-level specifications of an MZM based optoelectronic transceiver link. Link power budgets for NRZ, PAM-4 and PAM-8 signaling modulations are simulated at system-level. The optimal transmitter extinction ratio (ER) is derived based on the required receiver\u27s minimum optical modulation amplitude (OMA). A limiting receiver is fabricated in the IBM 130 nm CMOS process. By side- by-side wire-bonding to a commercial high-speed InGaAs/InP PIN photodiode, we demonstrate that the hybrid optoelectronic limiting receiver can achieve the bit error rate (BER) of 10-12 with a -6.7 dBm sensitivity at 4 Gb/s. A full-rate, 4-channel 29-1 length parallel PRBS is fabricated in the IBM 130 nm SiGe BiCMOS process. Together with a 10 GHz phase locked loop (PLL) designed from system architecture to transistor level design, the PRBS is demonstrated operating at more than 10 Gb/s. Lessons learned from high-speed PCB design, dealing with signal integrity issue regarding to the PCB transmission line are summarized

    Phase Noise in CMOS Phase-Locked Loop Circuits

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    Phase-locked loops (PLLs) have been widely used in mixed-signal integrated circuits. With the continuously increasing demand of market for high speed, low noise devices, PLLs are playing a more important role in communications. In this dissertation, phase noise and jitter performances are investigated in different types of PLL designs. Hot carrier and negative bias temperature instability effects are analyzed from simulations and experiments. Phase noise of a CMOS phase-locked loop as a frequency synthesizer circuit is modeled from the superposition of noises from its building blocks: voltage-controlled oscillator, frequency divider, phase-frequency detector, loop filter and auxiliary input reference clock. A linear time invariant model with additive noise sources in frequency domain is presented to analyze the phase noise. The modeled phase noise results are compared with the corresponding experimentally measured results on phase-locked loop chips fabricated in 0.5 m n-well CMOS process. With the scaling of CMOS technology and the increase of electrical field, MOS transistors have become very sensitive to hot carrier effect (HCE) and negative bias temperature instability (NBTI). These two reliability issues pose challenges to designers for designing of chips in deep submicron CMOS technologies. A new strategy of switchable CMOS phase-locked loop frequency synthesizer is proposed to increase its tuning range. The switchable PLL which integrates two phase-locked loops with different tuning frequencies are designed and fabricated in 0.5 µm CMOS process to analyze the effects under HCE and NBTI. A 3V 1.2 GHz programmable phase-locked loop frequency synthesizer is designed in 0.5 μm CMOS technology. The frequency synthesizer is implemented using LC voltage-controlled oscillator (VCO) and a low power dual-modulus prescaler. The LC VCO working range is from 900MHz to 1.4GHz. Current mode logic (CML) is used in designing high speed D flip-flop in the dual-modulus prescaler circuits for low power consumption. The power consumption of the PLL chip is under 30mW. Fully differential LC VCO is used to provide high oscillation frequency. A new design of LC VCO using carbon nanotube (CNT) wire inductor has been proposed. The PLL design using CNT-LC VCO shows significant improvement in phase noise due to high-Q LC circuit

    고속 시리얼 링크를 위한 고리 발진기를 기반으로 하는 주파수 합성기

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    학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 정덕균.In this dissertation, major concerns in the clocking of modern serial links are discussed. As sub-rate, multi-standard architectures are becoming predominant, the conventional clocking methodology seems to necessitate innovation in terms of low-cost implementation. Frequency synthesis with active, inductor-less oscillators replacing LC counterparts are reviewed, and solutions for two major drawbacks are proposed. Each solution is verified by prototype chip design, giving a possibility that the inductor-less oscillator may become a proper candidate for future high-speed serial links. To mitigate the high flicker noise of a high-frequency ring oscillator (RO), a reference multiplication technique that effectively extends the bandwidth of the following all-digital phase-locked loop (ADPLL) is proposed. The technique avoids any jitter accumulation, generating a clean mid-frequency clock, overall achieving high jitter performance in conjunction with the ADPLL. Timing constraint for the proper reference multiplication is first analyzed to determine the calibration points that may correct the existent phase errors. The weight for each calibration point is updated by the proposed a priori probability-based least-mean-square (LMS) algorithm. To minimize the time required for the calibration, each gain for the weight update is adaptively varied by deducing a posteriori which error source dominates the others. The prototype chip is fabricated in a 40-nm CMOS technology, and its measurement results verify the low-jitter, high-frequency clock generation with fast calibration settling. The presented work achieves an rms jitter of 177/223 fs at 8/16-GHz output, consuming 12.1/17-mW power. As the second embodiment, an RO-based ADPLL with an analog technique that addresses the high supply sensitivity of the RO is presented. Unlike prior arts, the circuit for the proposed technique does not extort the RO voltage headroom, allowing high-frequency oscillation. Further, the performance given from the technique is robust over process, voltage, and temperature (PVT) variations, avoiding the use of additional calibration hardware. Lastly, a comprehensive analysis of phase noise contribution is conducted for the overall ADPLL, followed by circuit optimizations, to retain the low-jitter output. Implemented in a 40-nm CMOS technology, the frequency synthesizer achieves an rms jitter of 289 fs at 8 GHz output without any injected supply noise. Under a 20-mVrms white supply noise, the ADPLL suppresses supply-noise-induced jitter by -23.8 dB.본 논문은 현대 시리얼 링크의 클락킹에 관여되는 주요한 문제들에 대하여 기술한다. 준속도, 다중 표준 구조들이 채택되고 있는 추세에 따라, 기존의 클라킹 방법은 낮은 비용의 구현의 관점에서 새로운 혁신을 필요로 한다. LC 공진기를 대신하여 능동 소자 발진기를 사용한 주파수 합성에 대하여 알아보고, 이에 발생하는 두가지 주요 문제점과 각각에 대한 해결 방안을 탐색한다. 각 제안 방법을 프로토타입 칩을 통해 그 효용성을 검증하고, 이어서 능동 소자 발진기가 미래의 고속 시리얼 링크의 클락킹에 사용될 가능성에 대해 검토한다. 첫번째 시연으로써, 고주파 고리 발진기의 높은 플리커 잡음을 완화시키기 위해 기준 신호를 배수화하여 뒷단의 위상 고정 루프의 대역폭을 효과적으로 극대화 시키는 회로 기술을 제안한다. 본 기술은 지터를 누적 시키지 않으며 따라서 깨끗한 중간 주파수 클락을 생성시켜 위상 고정 루프와 함께 높은 성능의 고주파 클락을 합성한다. 기준 신호를 성공적으로 배수화하기 위한 타이밍 조건들을 먼저 분석하여 타이밍 오류를 제거하기 위한 방법론을 파악한다. 각 교정 중량은 연역적 확률을 기반으로한 LMS 알고리즘을 통해 갱신되도록 설계된다. 교정에 필요한 시간을 최소화 하기 위하여, 각 교정 이득은 타이밍 오류 근원들의 크기를 귀납적으로 추론한 값을 바탕으로 지속적으로 제어된다. 40-nm CMOS 공정으로 구현된 프로토타입 칩의 측정을 통해 저소음, 고주파 클락을 빠른 교정 시간안에 합성해 냄을 확인하였다. 이는 177/223 fs의 rms 지터를 가지는 8/16 GHz의 클락을 출력한다. 두번째 시연으로써, 고리 발진기의 높은 전원 노이즈 의존성을 완화시키는 기술이 포함된 주파수 합성기가 설계되었다. 이는 고리 발진기의 전압 헤드룸을 보존함으로서 고주파 발진을 가능하게 한다. 나아가, 전원 노이즈 감소 성능은 공정, 전압, 온도 변동에 대하여 민감하지 않으며, 따라서 추가적인 교정 회로를 필요로 하지 않는다. 마지막으로, 위상 노이즈에 대한 포괄적 분석과 회로 최적화를 통하여 주파수 합성기의 저잡음 출력을 방해하지 않는 방법을 고안하였다. 해당 프로토타입 칩은 40-nm CMOS 공정으로 구현되었으며, 전원 노이즈가 인가되지 않은 상태에서 289 fs의 rms 지터를 가지는 8 GHz의 클락을 출력한다. 또한, 20 mVrms의 전원 노이즈가 인가되었을 때에 유도되는 지터의 양을 -23.8 dB 만큼 줄이는 것을 확인하였다.1 Introduction 1 1.1 Motivation 3 1.1.1 Clocking in High-Speed Serial Links 4 1.1.2 Multi-Phase, High-Frequency Clock Conversion 8 1.2 Dissertation Objectives 10 2 RO-Based High-Frequency Synthesis 12 2.1 Phase-Locked Loop Fundamentals 12 2.2 Toward All-Digital Regime 15 2.3 RO Design Challenges 21 2.3.1 Oscillator Phase Noise 21 2.3.2 Challenge 1: High Flicker Noise 23 2.3.3 Challenge 2: High Supply Noise Sensitivity 26 3 Filtering RO Noise 28 3.1 Introduction 28 3.2 Proposed Reference Octupler 34 3.2.1 Delay Constraint 34 3.2.2 Phase Error Calibration 38 3.2.3 Circuit Implementation 51 3.3 IL-ADPLL Implementation 55 3.4 Measurement Results 59 3.5 Summary 63 4 RO Supply Noise Compensation 69 4.1 Introduction 69 4.2 Proposed Analog Closed Loop for Supply Noise Compensation 72 4.2.1 Circuit Implementation 73 4.2.2 Frequency-Domain Analysis 76 4.2.3 Circuit Optimization 81 4.3 ADPLL Implementation 87 4.4 Measurement Results 90 4.5 Summary 98 5 Conclusions 99 A Notes on the 8REF 102 B Notes on the ACSC 105박

    Frequency Synthesizer Architectures for UWB MB-OFDM Alliance Application

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    High Performance Optical Transmitter Ffr Next Generation Supercomputing and Data Communication

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    High speed optical interconnects consuming low power at affordable prices are always a major area of research focus. For the backbone network infrastructure, the need for more bandwidth driven by streaming video and other data intensive applications such as cloud computing has been steadily pushing the link speed to the 40Gb/s and 100Gb/s domain. However, high power consumption, low link density and high cost seriously prevent traditional optical transceiver from being the next generation of optical link technology. For short reach communications, such as interconnects in supercomputers, the issues related to the existing electrical links become a major bottleneck for the next generation of High Performance Computing (HPC). Both applications are seeking for an innovative solution of optical links to tackle those current issues. In order to target the next generation of supercomputers and data communication, we propose to develop a high performance optical transmitter by utilizing CISCO Systems®\u27s proprietary CMOS photonic technology. The research seeks to achieve the following outcomes: 1. Reduction of power consumption due to optical interconnects to less than 5pJ/bit without the need for Ring Resonators or DWDM and less than 300fJ/bit for short distance data bus applications. 2. Enable the increase in performance (computing speed) from Peta-Flop to Exa-Flops without the proportional increase in cost or power consumption that would be prohibitive to next generation system architectures by means of increasing the maximum data transmission rate over a single fiber. 3. Explore advanced modulation schemes such as PAM-16 (Pulse-Amplitude-Modulation with 16 levels) to increase the spectrum efficiency while keeping the same or less power figure. This research will focus on the improvement of both the electrical IC and optical IC for the optical transmitter. An accurate circuit model of the optical device is created to speed up the performance optimization and enable co-simulation of electrical driver. Circuit architectures are chosen to minimize the power consumption without sacrificing the speed and noise immunity. As a result, a silicon photonic based optical transmitter employing 1V supply, featuring 20Gb/s data rate is fabricated. The system consists of an electrical driver in 40nm CMOS and an optical MZI modulator with an RF length of less than 0.5mm in 0.13&mu m SOI CMOS. Two modulation schemes are successfully demonstrated: On-Off Keying (OOK) and Pulse-Amplitude-Modulation-N (PAM-N N=4, 16). Both versions demonstrate signal integrity, interface density, and scalability that fit into the next generation data communication and exa-scale computing. Modulation power at 20Gb/s data rate for OOK and PAM-16 of 4pJ/bit and 0.25pJ/bit are achieved for the first time of an MZI type optical modulator, respectively
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