76,181 research outputs found

    DIA: A complexity-effective decoding architecture

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    Fast instruction decoding is a true challenge for the design of CISC microprocessors implementing variable-length instructions. A well-known solution to overcome this problem is caching decoded instructions in a hardware buffer. Fetching already decoded instructions avoids the need for decoding them again, improving processor performance. However, introducing such special--purpose storage in the processor design involves an important increase in the fetch architecture complexity. In this paper, we propose a novel decoding architecture that reduces the fetch engine implementation cost. Instead of using a special-purpose hardware buffer, our proposal stores frequently decoded instructions in the memory hierarchy. The address where the decoded instructions are stored is kept in the branch prediction mechanism, enabling it to guide our decoding architecture. This makes it possible for the processor front end to fetch already decoded instructions from the memory instead of the original nondecoded instructions. Our results show that using our decoding architecture, a state-of-the-art superscalar processor achieves competitive performance improvements, while requiring less chip area and energy consumption in the fetch architecture than a hardware code caching mechanism.Peer ReviewedPostprint (published version

    Racing to hardware-validated simulation

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    Processor simulators rely on detailed timing models of the processor pipeline to evaluate performance. The diversity in real-world processor designs mandates building flexible simulators that expose parts of the underlying model to the user in the form of configurable parameters. Consequently, the accuracy of modeling a real processor relies on both the accuracy of the pipeline model itself, and the accuracy of adjusting the configuration parameters according to the modeled processor. Unfortunately, processor vendors publicly disclose only a subset of their design decisions, raising the probability of introducing specification inaccuracies when modeling these processors. Inaccurately tuning model parameters deviates the simulated processor from the actual one. In the worst case, using improper parameters may lead to imbalanced pipeline models compromising the simulation output. Therefore, simulation models should be hardware-validated before using them for performance evaluation. As processors increase in complexity and diversity, validating a simulator model against real hardware becomes increasingly more challenging and time-consuming. In this work, we propose a methodology for validating simulation models against real hardware. We create a framework that relies on micro-benchmarks to collect performance statistics on real hardware, and machine learning-based algorithms to fine-tune the unknown parameters based on the accumulated statistics. We overhaul the Sniper simulator to support the ARM AArch64 instruction-set architecture (ISA), and introduce two new timing models for ARM-based in-order and out-of-order cores. Using our proposed simulator validation framework, we tune the in-order and out-of-order models to match the performance of a real-world implementation of the Cortex-A53 and Cortex-A72 cores with an average error of 7% and 15%, respectively, across a set of SPEC CPU2017 benchmarks

    Aggregate effect on the concrete cone capacity of an undercut anchor under quasi-static tensile load

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    In the last decades, fastening systems have become an essential part of the construction industry. Post-installed mechanical anchors are frequently used in concrete members to connect them with other load bearing structural members, or to attach appliances. Their performance is limited by the concrete related failure modes which are highly influenced by the concrete mix design. This paper aims at investigating the effect that different aggregates used in the concrete mix have on the capacity of an undercut anchor under tensile quasi-static loading. Three concrete batches were cast utilising three different aggregate types. For two concrete ages (28 and 70 days), anchor tensile capacity and concrete properties were obtained. Concrete compressive strength, fracture energy and elastic modulus are used to normalize and compare the undercut anchor concrete tensile capacity employing some of the most widely used prediction models. For a more insightful comparison, a statistical method that yields also scatter information is introduced. Finally, the height and shape of the concrete cones are compared by highly precise and objective photogrammetric means

    Beliefs Underlying Employee Readiness to Support a Building Relocation: A Theory of Planned Behavior Perspective

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    The purpose of this research was to examine the utility of the Theory of Planned Behavior (TPB) as a framework for understanding employee readiness for change. One of the major advantages of the TPB approach is its ability to identify the underlying beliefs that distinguish between those who intend and do not intend to perform the behavior under investigation. In the present study, the extent to which a sample of local government employees intended to carry out activities during a 6-month period that were supportive of their organization's relocation to new premises was examined. An elicitation study (N = 18) determined salient beliefs relating to the relocation. For the main study, 149 participants completed a questionnaire that assessed their behavioral, normative, and control beliefs in regards to the change event. A series of MANOVAs revealed statistically significant differences between employees with moderate compared to high intentions to engage in changesupportive behaviors on a range of beliefs. Implications of these findings for designing change management strategies that help foster readiness for change are discussed
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