FSMD-Based Hardware Accelerators for FPGAs

Current VLSI technology allows the design of sophisticated digital systems with escalated demands in performance and power/energy consumption. The annual increase of chip complexity is 58%, while human designers productivity increase is limited to 21 % per annum (ITRS, 2011). The growing technology-productivity gap is probably the most importan

FPGA Implementation of digital controller for shunt active power filter to reduce harmonics and reactive power

Most of the pollution issues created in power systems are due to the non-linear characteristics and fast switching of power electronic equipment. Power quality issues are becoming stronger because sensitive equipment will be more sensitive for market competition reasons, equipment will continue polluting the system more and more due to cost increase caused by the built-in compensation and sometimes for the lack of enforced regulations. Efficiency and cost are considered today almost at the same level. Active power filters have been developed over the years to solve these problems to improve power quality. Among which shunt active power filter is used to eliminate and load current harmonics and reactive power compensation. The active power filter (APF) is implemented with PWM based current controlled voltage source inverter (VSI). This VSI switching signals are generated through proposed three-level hysteresis current controller (HCC) that achieves significant reduction in the magnitude and variation of the switching frequency; it is indicating improved performance compared to 2-level HCC. The shunt APLC system is modeled and investigated under different unbalanced non-linear load conditions using MATLAB programs. The simulation results reveal that the active power filter is effectively compensating the current harmonics and reactive power at point of common coupling. The active power line conditioner system is in compliance with IEEE 519 and IEC 61000-3 recommended harmonic standards. Due to non-linear characteristics the load current gets distorted which causes undesirable effects like heating, equipment damages, EMI effects etc. in power network. The active power filter (APF) is the best solution for eliminating the harmonics caused by the non-linear loads. This work presents the three-phase four-wire active filter for power line conditioning (PLC) to improve power quality in the distribution network and implementation of a digitally controlled APF. Designed in Hardware Description Language (VHDL or VERILOG), the controller becomes independent of process technology. Synchronous reference frame is used for generation of reference current. PI currents algorithm and hysteresis current controller (HCC) together is written in VHDL code and is implemented using FPGA platform. Various simulation results are presented under steady state and transient state condition and performance is analyzed. Simulation results obtained shows that the performance of three phase system with APF is found to be better and digital controller add a new aspect for the controller from low cost, high speed and hardware implementation point.PWM and hysteresis based current control is used to obtain the switching signals to the voltage source inverter(VSI)

FPGA Based Active Power Filter for Harmonics Mitigation

The application of power electronics devices such as arc furnaces, adjustable speed drives, computer power supplies etc. are some typical non-linear characteristic loads used in most of the industrial applications and are increasing rapidly due to technical improvements of semiconductor devices, digital controller and flexibility in controlling the power usage. The use of the above power electronic devices in power distribution system gives rise to harmonics and reactive power disturbances. The harmonics and reactive power cause a number of undesirable effects like heating, equipment damage and Electromagnetic Interference effects in the power system. The conventional method to mitigate the harmonics and reactive power compensation is by using passive LC filters but this method has drawbacks like large size, resonance problem and fixed compensation behaviour etc., so this solution becomes ineffective [7]. Subsequently, the active power filter (APF) comes in to the picture, which gives promising solution to compensate for the above adverse effects of harmonics and reactive power simultaneously by using suitable control algorithms. Different APF topology has proposed by many authors, such as series, shunt and hybrid type and these may be based on current source or voltage source. Series APF is used to compensate the voltage harmonics and shunt type for current harmonics. As non-linear loads are injecting current harmonics to the power system, the suitable choice to eliminate current harmonics and reactive power is voltage source shunt APF. To extract the fundamental component of source current synchronous reference frame (SRF) theory [12] is suitable because of its easy mathematical calculation compared to p-q (Instantaneous theory) control algorithm. Further, switching signals to drive the VSI of the APF two popular control strategies namely hysteresis current controller (HCC) and adaptive hysteresis current controller (Adaptive- HCC) are used. Also fuzzy logic controller is used generate the reference current and maintain the DC side capacitor voltage almost constant. A comparative study of the performances of two current control strategies HCC and Adaptive-HCC is carried out in this thesis and it has been observed from simulation results that AHCC exhibits superior performance compared to the HCC. These current controllers have some disadvantages such as high cost, slow response, and large size etc., during real-time implementation. But by using digital controller one can avail the advantages like reconfigurable hardware designs, low cost developments, selection of bit width according to applications etc. In this thesis, a PI current control algorithm together with a hysteresis current controller is written in VHDL code and then is implemented using FPGA platform

Model-based specification and design of large-scale embedded signal processing systems

In the digital part of large-scale phase array radio telescopes, the dominant streaming signal processing part is configured at run-time through a reactive and decentralized control and monitoring part. Interfacing and synchronizing these two parts without altering the behavior and performance of the dominant signal processing part is an issue when they are first considered in isolation. To address this issue before going to implementation, we propose to raise the level of abstraction, by expressing system-level specifications (in terms of application, architecture, and mapping) based on models. In the application model, the model of the control part and the model of the signal processing part are synchronized based on a notion of time that is known only to the control part. In the architecture model, the control model has a tree-like structure, whose leave nodes are interfaced with the computational nodes in the signal processing part. The mapping is based on iterative and interactive transformations that lead to an implementation-level specification, from where we consider that different implementation tools can take over to implement different parts of the system.UBL - phd migration 201

Design and Implementation in FPGA Technology of a High-Performance Block Scan and Map to Symbols Module for CCSDS-122 Image Data Compression

Η τηλεπισκόπιση αποτελεί ακρογωνιαίο λίθο των σύγχρονων τεχνολογιών παρατήρησης. Τα σύγχρονα διαστημικά οπτικά όργανα απεικόνισης υψηλής ανάλυσης και υψηλής ταχύ¬τητας οδηγούν σε εκρηκτική αύξηση του όγκου δεδομένων και επιβάλλουν ρυθμούς δεδο¬μένων της τάξης των αρκετών Gbps. Αυτό έρχεται σε αντίθεση με τους περιορισμένους πόρους αποθήκευσης δεδομένων εν πτήσει και το περιορισμένο εύρος ζώνης κατερχό¬μενης ζεύξης, καθιστώντας την συμπίεση δεδομένων εικόνας μια βασική υποστηρικτική τεχνολογία επεξεργασίας δεδομένων εν πτήσει. Η Συμβουλευτική Επιτροπή για Συστήματα Διαστημικών Δεδομένων (CCSDS) εξέδωσε το 2005 ένα συνιστώμενο πρότυπο για τη συμπίεση δεδομένων εικόνας (Image Data Compression – IDC) (CCSDS-122.0-B-1), το οποίο ορίζει έναν αλγόριθμο συμπίεσης δεδομένων 2D εικόνας που βασίζεται σε μετασχηματισμό, σχεδιασμένο ειδικά για χρήση εν πτήσει σε διαστημική πλατφόρμα ή ωφέλιμο φορτίο. Μια επέκταση αυτού του προτύπου, CCSDS-122.0-B-2, εκδόθηκε το 2017 για να οριστούν όλες οι απαραίτητες τροποποιήσεις για την υποστήριξη ενός συνιστώμενου προτύπου για τον μετασχηματισμό φασματικής προεπεξεργασίας για πολυφασματική και υπερφασματική συμπίεση εικόνας. Η δεύτερη έκδοση υποστηρίζει εικόνες υψηλότερου δυναμικού εύρους και για μεγαλύτερα μεγέθη λέξεων. Ένα άλλο συνιστώμενο πρότυπο, το CCSDS-122.1-B-1, εκδόθηκε ταυτόχρονα το 2017 για τον καθορισμό των αποκλειστικών φασματικών μετασχηματισμών προεπεξεργασίας. Στην παρούσα διπλωματική εργασία, εισάγεται μια νέα αρχιτεκτονική υψηλής απόδοσης και η αντίστοιχη υλοποίησή της σε τεχνολογία FPGA μίας υπομονάδας κλειδί του αλγορίθμου CCSDS-¬IDC, της υπομονάδας του Bit Plane Encoder που πραγματοποιεί τη διαδικασία Block Scan and Map to Symbols, που στην συνέχεια θα ονομάζουμε μονάδα BSMS. H νέα υλοποίηση βασίζεται επίσης στην εκμετάλλευση της παραλληλίας του προτεινόμενου αλγορίθμου, ενώ ταυτόχρονα επιτυγχάνει την επεξεργασία ενός δείγματος δεδομένων ανά κύκλο.Remote sensing is recognized as a cornerstone monitoring technology. The latest high ¬resolution and high-speed space-borne imagers provide an explosive growth in data volume and instrument data rates in the range of several Gbps. This competes with the limited on-board storage resources and downlink bandwidth, making image data compression a mission-critical on-board processing task. The Consultative Committee for Space Data Systems (CCSDS) issued in 2005 a recommended standard for Image Data Compression (IDC) (CCSDS-122.0-B-1) which defines a transform-based 2D image data compression algorithm designed specifically for use on-board in a space platform or a payload. An extension of this standard, CCSDS-122.0-B-2, was issued in 2017 to define all necessary modifications to support a recommended standard for Spectral Preprocessing Transform for Multispectral and Hyperspectral Image Compression. The new issue supports images of higher dynamic range and for larger word sizes. Another recommended standard, CCSDS-122.1-B-1, was issued concurrently in 2017 to define the dedicated spectral preprocessing transforms. In this master thesis is introduced a new high-performance architecture and implementation in FPGA technology for a key-part of the CCSDS-IDC algorithm, the submodule of the Bit Plane Encoder which implements the Block Scan and Map to Symbols process, hereafter termed BSMS, is described. The proposed architecture implementation is based on the standard’s existing parallelism, while at the same time introduces new attributes of speed, since it can process one data sample per one clock cycle and thus outperforms previous implementations that required more clock cycles

H-calculus : session types for hardware analysis and well-definedness

Dissertação (mestrado)—Universidade de Brasília, Instituto de Ciências Exatas, Departamento de Ciência da Computação, 2021.Síntese de alto nível é considerada o próximo passo lógico em design de hardware, mas os resultados, em geral, ainda não são tão bons quanto ao que a indústria necessita. Conjecturamos que a falta de uma representação de hardware adequada, criada espe cificamente para análise automática de hardware, é um dos principais motivos pelos quais os resultados são difíceis de otimizar. Apresentamos o cálculo-h, cálculo tipado que usa tipos de sessão temporal para bem-definição e análise de hardware. Intro duzimos os conceitos principais, formalizamos suas definições, demonstramos como a análise por meio de tipos funciona, e discutimos sua utilidade na síntese de alto nível.High-Level Synthesis has been considered the next logical step for hardware design, but results are, in general, still not as good as the industry requires. We conjecture that the lack of a proper hardware representation crafted specifically for automatic hardware analysis is one of the key reasons why results are hard to optimize. We present the h-calculus, typed calculus that uses temporal session types for hardware well-definedness and analysis. We introduce the key concepts, formalize their defi nitions, demonstrate how analysis through types works, and discuss its utility within High-Level Synthesis

Efficient implementation of video processing algorithms on FPGA

The work contained in this portfolio thesis was carried out as part of an Engineering Doctorate (Eng.D) programme from the Institute for System Level Integration. The work was sponsored by Thales Optronics, and focuses on issues surrounding the implementation of video processing algorithms on field programmable gate arrays (FPGA). A description is given of FPGA technology and the currently dominant methods of designing and verifying firmware. The problems of translating a description of behaviour into one of structure are discussed, and some of the latest methodologies for tackling this problem are introduced. A number of algorithms are then looked at, including methods of contrast enhancement, deconvolution, and image fusion. Algorithms are characterised according to the nature of their execution flow, and this is used as justification for some of the design choices that are made. An efficient method of performing large two-dimensional convolutions is also described. The portfolio also contains a discussion of an FPGA implementation of a PID control algorithm, an overview of FPGA dynamic reconfigurability, and the development of a demonstration platform for rapid deployment of video processing algorithms in FPGA hardware

Mecanismos de suporte para MAC 802.11p determinística

Mestrado em Engenharia Eletrónica e TelecomunicaçõesTransportation systems play an extremely important role in modern society. A huge research e ort has been devoted to this eld in the past few years making them safer cleaner and more e cient, originating the so-called Intelligent Transportation Systems (ITS). While some of the enabling technologies are entering their mature phase, there are still many open problems that must be solved before such systems can be e ectively leveraged. Specifically, the medium access is regarded as being one of the most challenging issues to solve in order to provide dependable wireless communications in vehicular networks [BUSB09]. The standard protocols have been shown to fail in addressing this issue and some possible solutions are being proposed, but despite the di culty of correctly modelling the channel dynamics, most work on MAC protocols for real-time vehicular communications has been performed under simulated environments, using simplistic assumptions that do not necessarily hold in a read environment. The implementation of a deterministic MAC scheme is hampered by the fact that commercial devices do not allow modi cations to the standard MAC mechanism, and the development of a device from scratch to implement one Medium Access Control (MAC) scheme is an extremely laborious endeavour. However, over the last few years, the IT2S platform for vehicular communication has been developed and is now in a stage that allows implementation and testing of new solutions for the vehicular communications environment. It is a exible platform that allows modi cation to be made in any layer of the communication stack and therefore suited to be adapted for the implementation of new MAC schemes. This work presents an overview of MAC mechanisms capable of providing deterministic real-time access and assesses the features a communications device must include in order to allow the implementation of these mechanisms. It then proposes an implementation of such as device based on the existing IT2S plaform. A exible solution was obtained that allows all the studied MAC schemes to be implemented purely in software, with no modi cations required to the hardware mechanisms, lowering the needed amount of skills required to perform a working implementation of a novel MAC scheme. The performance of the solution was also found to be appropriate for the required uses. It is now possible to create test beds for new MAC schemes and perform more concrete and accurate analysis of their performance.Os meios de transporte têm um papel preponderante na sociedade moderna. Muito esforço de investigação tem sido dedicada e este campo nos últimos anos, com vista a tornar estes meios mais limpos, seguros e eficientes, originado os chamados Sistemas de Transporte Inteligentes (ITS). Enquanto algumas das tecnologias base estão já prontas a ser utilizadas, ainda existem problemas a ser resolvidos antes de se poder utilizar todo o potencial destes sistemas. Um problema específico, o acesso ao meio, é atualmente considerado um dos mais desa antes em termos de investigação e que detém ainda uma quantidade interessante de problemas a ser resolvidos para que se possa depender de comunicações sem fios em ambientes veiculares. Estudos provaram que os protocolos standard nãoo resolvem este problema e têm sido propostas soluções, Mas apesar da dificuldade de modelar corretamente a dinâmica do canal, a maior parte das análises tem sido realizada em ambientes de simulação, com assunçõess simplistas que não correspondem necessariamente ao ambiente real. A implementação de um mecanismo de acesso ao meio determinístico é dificultada pelo facto de que os dispositivos comerciais não permitem modificações aos mecanismos standard e o desenvolvimento de um dispositivo de raiz que implemente o mecanismo proposto ser extremamente trabalhoso. No entanto,ao longo dos últimos anos tem sido desenvolvida a plataforma de comunicações veiculares IT2S, que atingiu agora uma fase que permite a sua utilização para implementar e testar novas soluções para ambientes veiculares. Trata-se de uma plataforma flexível que permite a realização de modificações em qualquer camada da pilha protocolar, portanto passível de ser adaptada para a implementação de novos mecanismos de acesso ao meio. Este trabalho apresenta uma perspetiva alargada dos mecanismos de acesso ao meio determinísticos propostos na literatura e estuda quais as características necessárias que um dispositivo de comunicação precisa fornecer para os poder implementar. Segue-se então uma proposta de implementação de um tal dispositivo, baseada na plataforma IT2S. Foi possível obter uma solução flexível o suficiente para implementar todos os mecanismos estudados recorrendo apenas a software, sem necessidade de alterações ao hardware, baixando a fasquia da dificuldade na criação de uma implementação prática de um mecanismo de acesso ao meio. A solução foi testada e a desempenho considerada adequada para as possíveis utilizações. É agora possível criar bancadas de teste para novos mecanismos de acesso ao meio e executar análises mais concretas e precisas da sua desempenho

High-level synthesis of dataflow programs for heterogeneous platforms:design flow tools and design space exploration

The growing complexity of digital signal processing applications implemented in programmable logic and embedded processors make a compelling case the use of high-level methodologies for their design and implementation. Past research has shown that for complex systems, raising the level of abstraction does not necessarily come at a cost in terms of performance or resource requirements. As a matter of fact, high-level synthesis tools supporting such a high abstraction often rival and on occasion improve low-level design. In spite of these successes, high-level synthesis still relies on programs being written with the target and often the synthesis process, in mind. In other words, imperative languages such as C or C++, most used languages for high-level synthesis, are either modified or a constrained subset is used to make parallelism explicit. In addition, a proper behavioral description that permits the unification for hardware and software design is still an elusive goal for heterogeneous platforms. A promising behavioral description capable of expressing both sequential and parallel application is RVC-CAL. RVC-CAL is a dataflow programming language that permits design abstraction, modularity, and portability. The objective of this thesis is to provide a high-level synthesis solution for RVC-CAL dataflow programs and provide an RVC-CAL design flow for heterogeneous platforms. The main contributions of this thesis are: a high-level synthesis infrastructure that supports the full specification of RVC-CAL, an action selection strategy for supporting parallel read and writes of list of tokens in hardware synthesis, a dynamic fine-grain profiling for synthesized dataflow programs, an iterative design space exploration framework that permits the performance estimation, analysis, and optimization of heterogeneous platforms, and finally a clock gating strategy that reduces the dynamic power consumption. Experimental results on all stages of the provided design flow, demonstrate the capabilities of the tools for high-level synthesis, software hardware Co-Design, design space exploration, and power optimization for reconfigurable hardware. Consequently, this work proves the viability of complex systems design and implementation using dataflow programming, not only for system-level simulation but real heterogeneous implementations