78 research outputs found
Design of adaptive analog filters for magnetic front-end read channels
Esta tese estuda o projecto e o comportamento de filtros em tempo contínuo de
muito-alta-frequência. A motivação deste trabalho foi a investigação de soluções de filtragem
para canais de leitura em sistemas de gravação e reprodução de dados em suporte
magnético, com custos e consumo (tamanho total inferior a 1 mm2 e consumo inferior a
1mW/polo), inferiores aos circuitos existentes. Nesse sentido, tal como foi feito neste
trabalho, o rápido desenvolvimento das tecnologias de microelectrónica suscitou esforços
muito significativos a nível mundial com o objectivo de se investigarem novas técnicas
de realização de filtros em circuito integrado monolítico, especialmente em tecnologia
CMOS (Complementary Metal Oxide Semiconductor). Apresenta-se um estudo comparativo
a diversos níveis hierárquicos do projecto, que conduziu à realização e caracterização
de soluções com as características desejadas.
Num primeiro nível, este estudo aborda a questão conceptual da gravação e transmissão
de sinal bem como a escolha de bons modelos matemáticos para o tratamento da
informação e a minimização de erro inerente às aproximações na conformidade aos princípios
físicos dos dispositivos caracterizados.
O trabalho principal da tese é focado nos níveis hierárquicos da arquitectura do
canal de leitura e da realização em circuito integrado do seu bloco principal – o bloco de
filtragem. Ao nível da arquitectura do canal de leitura, apresenta-se um estudo alargado
sobre as metodologias existentes de adaptação de sinal e recuperação de dados em suporte
magnético. Este desígnio aparece no âmbito da proposta de uma solução de baixo custo,
baixo consumo, baixa tensão de alimentação e baixa complexidade, alicerçada em tecnologia
digital CMOS, para a realização de um sistema DFE (Decision Feedback Equalization)
com base na igualização de sinal utilizando filtros integrados analógicos em tempo
contínuo.
Ao nível do projecto de realização do bloco de filtragem e das técnicas de implementação
de filtros e dos seus blocos constituintes em circuito integrado, concluiu-se que
a técnica baseada em circuitos de transcondutância e condensadores, também conhecida como filtros gm-C (ou transcondutância-C), é a mais adequada para a realização de filtros
adaptativos em muito-alta-frequência. Definiram-se neste nível hierárquico mais baixo,
dois subníveis de aprofundamento do estudo no âmbito desta tese, nomeadamente: a pesquisa
e análise de estruturas ideais no projecto de filtros recorrendo a representações no
espaço de estados; e, o estudo de técnicas de realização em tecnologia digital CMOS de
circuitos de transcondutância para a implementação de filtros integrados analógicos em
tempo contínuo.
Na sequência deste estudo, apresentam-se e comparam-se duas estruturas de filtros
no espaço de estados, correspondentes a duas soluções alternativas para a realização de
um igualador adaptativo realizado por um filtro contínuo passa-tudo de terceira ordem,
para utilização num canal de leitura de dados em suporte magnético.
Como parte constituinte destes filtros, apresenta-se uma técnica de realização de
circuitos de transcondutância, e de realização de condensadores lineares usando matrizes
de transístores MOSFET para processamento de sinal em muito-alta-frequência realizada
em circuito integrado usando tecnologia digital CMOS submicrométrica. Apresentam-se
métodos de adaptação automática capazes de compensar os erros face aos valores nominais
dos componentes, devidos às tolerâncias inerentes ao processo de fabrico, para os
quais apresentamos os resultados de simulação e de medição experimental obtidos.
Na sequência deste estudo, resultou igualmente a apresentação de um circuito passível
de constituir uma solução para o controlo de posicionamento da cabeça de leitura
em sistemas de gravação/reprodução de dados em suporte magnético. O bloco proposto
é um filtro adaptativo de primeira ordem, com base nos mesmos circuitos de transcondutância
e técnicas de igualação propostos e utilizados na implementação do filtro adaptativo
de igualação do canal de leitura.
Este bloco de filtragem foi projectado e incluído num circuito integrado (Jaguar) de
controlo de posicionamento da cabeça de leitura realizado para a empresa ATMEL em
Colorado Springs, e incluído num produto comercial em parceria com uma empresa escocesa
utilizado em discos rígidos amovíveis.This thesis studies the design and behavior of continuous-time very-high-frequency
filters. The motivation of this work was the search for filtering solutions for the readchannel
in recording and reproduction of data on magnetic media systems, with costs and
consumption (total size less than 1 mm2 and consumption under 1mW/pole), lower than
the available circuits. Accordingly, as was done in this work, the rapid development of
microelectronics technology raised very significant efforts worldwide in order to investigate
new techniques for implementing such filters in monolithic integrated circuit, especially
in CMOS technology (Complementary Metal Oxide Semiconductor). We present
a comparative study on different hierarchical levels of the project, which led to the realization
and characterization of solutions with the desired characteristics.
In the first level, this study addresses the conceptual question of recording and
transmission of signal and the choice of good mathematical models for the processing of
information and minimization of error inherent in the approaches and in accordance with
the principles of the characterized physical devices.
The main work of this thesis is focused on the hierarchical levels of the architecture
of the read channel and the integrated circuit implementation of its main block - the filtering
block. At the architecture level of the read channel this work presents a comprehensive
study on existing methodologies of adaptation and signal recovery of data on
magnetic media. This project appears in the sequence of the proposed solution for a lowcost,
low consumption, low voltage, low complexity, using CMOS digital technology for
the performance of a DFE (Decision Feedback Equalization) based on the equalization of
the signal using integrated analog filters in continuous time.
At the project level of implementation of the filtering block and techniques for implementing
filters and its building components, it was concluded that the technique based
on transconductance circuits and capacitors, also known as gm-C filters is the most appropriate
for the implementation of very-high-frequency adaptive filters. We defined in
this lower level, two sub-levels of depth study for this thesis, namely: research and analysis
of optimal structures for the design of state-space filters, and the study of techniques for the design of transconductance cells in digital CMOS circuits for the implementation
of continuous time integrated analog filters.
Following this study, we present and compare two filtering structures operating in
the space of states, corresponding to two alternatives for achieving a realization of an
adaptive equalizer by the use of a continuous-time third order allpass filter, as part of a
read-channel for magnetic media devices.
As a constituent part of these filters, we present a technique for the realization of
transconductance circuits and for the implementation of linear capacitors using arrays of
MOSFET transistors for signal processing in very-high-frequency integrated circuits using
sub-micrometric CMOS technology. We present methods capable of automatic adjustment
and compensation for deviation errors in respect to the nominal values of the
components inherent to the tolerances of the fabrication process, for which we present
the simulation and experimental measurement results obtained.
Also as a result of this study, is the presentation of a circuit that provides a solution
for the control of the head positioning on recording/playback systems of data on magnetic
media. The proposed block is an adaptive first-order filter, based on the same transconductance
circuits and equalization techniques proposed and used in the implementation
of the adaptive filter for the equalization of the read channel.
This filter was designed and included in an integrated circuit (Jaguar) used to control
the positioning of the read-head done for ATMEL company in Colorado Springs, and
part of a commercial product used in removable hard drives fabricated in partnership with a Scottish company
Available Techniques for Magnetic Hard Disk Drive Read Channel Equalization
This paper presents an extensive, non-exhaustive, study of available hard disk drive read channel equalization techniques used in the storage and readback of magnetically stored information. The physical elements and basic principles of the storage processes are introduced together with the basic theoretical definitions and models. Both read and write processes in magnetic storage are explained along with the definition of simple key concepts such as user bit density, intersymbol interference, linear and areal density, read head pulse response models, and coding algorithm
Design of a fully digital multi-level decision feedback equalization chip
Master'sMASTER OF ENGINEERIN
Convergence study for adaptive allpass filtering
Adaptive filtering may be applied in areas where an optimal filtering algorithm
may not be known a-priori and where the filtering operation may be non-stationary. This
field, or more generally, the field of adaptive systems, is one which may be regarded as
mature, having been the subject of considerable research effort in the areas of control and
signal processing for almost four decades.
DFE (decision feedback equalization) in various forms has been proposed for detection
on magnetic recording channel. An allpass filter is an alternative to the FIR (finite
impulse response) forward equalizer which is normally implemented with DFE. This is
because the allpass filter is a lower power and complexity alternative, though its behavior
and performance are not very well understood yet.
Here, an allpass structure implemented as first and second order IIR (infinite
impulse response) filters is examined. Convergence for the LMS (least mean square) adaptation
algorithm is studied and, moreover, some convergence conditions and bounds are
developed, similarly to the well known FIR case. This thesis provides an useful analytical
study of convergence of IIR adaptive filtering. This is accomplished by a systematic approximation
of the covariance terms of the adaptive coefficients. The range of the step-size
parameter of the LMS algorithm is developed under some simplifying assumptions. All
the results obtained are verified by simulation (Matlab and C routines are used)
Hybrid NRZ/Multi-Tone Signaling for High-Speed Low-Power Wireline Transceivers
Over the past few decades, incessant growth of Internet networking traffic and High-Performance Computing (HPC) has led to a tremendous demand for data bandwidth. Digital communication technologies combined with advanced integrated circuit scaling trends have enabled the semiconductor and microelectronic industry to dramatically scale the bandwidth of high-loss interfaces such as Ethernet, backplane, and Digital Subscriber Line (DSL). The key to achieving higher bandwidth is to employ equalization technique to compensate the channel impairments such as Inter-Symbol Interference (ISI), crosstalk, and environmental noise. Therefore, todayâs advanced input/outputs (I/Os) has been equipped with sophisticated equalization techniques to push beyond the uncompensated bandwidth of the system. To this end, process scaling has continually increased the data processing capability and improved the I/O performance over the last 15 years. However, since the channel bandwidth has not scaled with the same pace, the required signal processing and equalization circuitry becomes more and more complicated. Thereby, the energy efficiency improvements are largely offset by the energy needed to compensate channel impairments. In this design paradigm, re-thinking about the design strategies in order to not only satisfy the bandwidth performance, but also to improve power-performance becomes an important necessity. It is well known in communication theory that coding and signaling schemes have the potential to provide superior performance over band-limited channels. However, the choice of the optimum data communication algorithm should be considered by accounting for the circuit level power-performance trade-offs. In this thesis we have investigated the application of new algorithm and signaling schemes in wireline communications, especially for communication between microprocessors, memories, and peripherals. A new hybrid NRZ/Multi-Tone (NRZ/MT) signaling method has been developed during the course of this research. The system-level and circuit-level analysis, design, and implementation of the proposed signaling method has been performed in the frame of this work, and the silicon measurement results have proved the efficiency and the robustness of the proposed signaling methodology for wireline interfaces. In the first part of this work, a 7.5 Gb/s hybrid NRZ/MT transceiver (TRX) for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40 nm CMOS technology. Reducing the complexity of the equalization circuitry on the receiver (RX) side, the proposed architecture achieves 1 pJ/bit link efficiency for a MDB channel bearing 45 dB loss at 2.5 GHz. The measurement results of the first prototype confirm that NRZ/MT serial data TRX can offer an energy-efficient solution for MDB memory interfaces. Motivated by the satisfying results of the first prototype, in the second phase of this research we have exploited the properties of multi-tone signaling, especially orthogonality among different sub-bands, to reduce the effect of crosstalk in high-dense wireline interconnects. A four-channel transceiver has been implemented in a standard CMOS 40 nm technology in order to demonstrate the performance of NRZ/MT signaling in presence of high channel loss and strong crosstalk noise. The proposed system achieves 1 pJ/bit power efficiency, while communicating over a MDB memory channel at 36 Gb/s aggregate data rate
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