An empirical evaluation of High-Level Synthesis languages and tools for database acceleration

High Level Synthesis (HLS) languages and tools are emerging as the most promising technique to make FPGAs more accessible to software developers. Nevertheless, picking the most suitable HLS for a certain class of algorithms depends on requirements such as area and throughput, as well as on programmer experience. In this paper, we explore the different trade-offs present when using a representative set of HLS tools in the context of Database Management Systems (DBMS) acceleration. More specifically, we conduct an empirical analysis of four representative frameworks (Bluespec SystemVerilog, Altera OpenCL, LegUp and Chisel) that we utilize to accelerate commonly-used database algorithms such as sorting, the median operator, and hash joins. Through our implementation experience and empirical results for database acceleration, we conclude that the selection of the most suitable HLS depends on a set of orthogonal characteristics, which we highlight for each HLS framework.Peer ReviewedPostprint (author’s final draft

Hardware Architectures of Visible Light Communication Transmitter and Receiver for Beacon-based Indoor Positioning Systems

High-speed applications of Visible Light Communications have been presented recently in which response times of photodiode-based VLC receivers are critical points. Typical VLC receiver routines, such as soft-decoding of run-length limited (RLL) codes and FEC codes was purely processed on embedded firmware, and potentially cause bottleneck at the receiver. To speed up the performance of receivers, ASIC-based VLC receiver could be the solution. Unfortunately, recent works on soft-decoding of RLL and FEC have shown that they are bulky and time-consuming computations. This causes hardware implementation of VLC receivers becomes heavy and unrealistic. In this paper, we introduce a compact Polar-code-based VLC receivers. in which flicker mitigation of the system can be guaranteed even without RLL codes. In particular, we utilized the centralized bit-probability distribution of a pre-scrambler and a Polar encoder to create a non-RLL flicker mitigation solution. At the receiver, a 3-bit soft-decision filter was implemented to analyze signals received from the VLC channel to extract log-likelihood ratio (LLR) values and feed them to the Polar decoder. Therefore, the proposed receiver could exploit the soft-decoding of the Polar decoder to improve the error-correction performance of the system. Due to the non-RLL characteristic, the receiver has a preeminent code-rate and a reduced complexity compared with RLL-based receivers. We present the proposed VLC receiver along with a novel very-large-scale integration (VLSI) architecture, and a synthesis of our design using FPGA/ASIC synthesis tools

Multiple bit error correcting architectures over finite fields

This thesis proposes techniques to mitigate multiple bit errors in GF arithmetic circuits. As GF arithmetic circuits such as multipliers constitute the complex and important functional unit of a crypto-processor, making them fault tolerant will improve the reliability of circuits that are employed in safety applications and the errors may cause catastrophe if not mitigated. Firstly, a thorough literature review has been carried out. The merits of efficient schemes are carefully analyzed to study the space for improvement in error correction, area and power consumption. Proposed error correction schemes include bit parallel ones using optimized BCH codes that are useful in applications where power and area are not prime concerns. The scheme is also extended to dynamically correcting scheme to reduce decoder delay. Other method that suits low power and area applications such as RFIDs and smart cards using cross parity codes is also proposed. The experimental evaluation shows that the proposed techniques can mitigate single and multiple bit errors with wider error coverage compared to existing methods with lesser area and power consumption. The proposed scheme is used to mask the errors appearing at the output of the circuit irrespective of their cause. This thesis also investigates the error mitigation schemes in emerging technologies (QCA, CNTFET) to compare area, power and delay with existing CMOS equivalent. Though the proposed novel multiple error correcting techniques can not ensure 100% error mitigation, inclusion of these techniques to actual design can improve the reliability of the circuits or increase the difficulty in hacking crypto-devices. Proposed schemes can also be extended to non GF digital circuits

NASA Space Engineering Research Center for VLSI systems design

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design

Index to 1984 NASA Tech Briefs, volume 9, numbers 1-4

Short announcements of new technology derived from the R&D activities of NASA are presented. These briefs emphasize information considered likely to be transferrable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. This index for 1984 Tech B Briefs contains abstracts and four indexes: subject, personal author, originating center, and Tech Brief Number. The following areas are covered: electronic components and circuits, electronic systems, physical sciences, materials, life sciences, mechanics, machinery, fabrication technology, and mathematics and information sciences

Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning

Existing scrubbing techniques for SEU mitigation on FPGAs do not guarantee an error-free operation after SEU recovering if the affected configuration bits do belong to feedback loops of the implemented circuits. In this paper, we a) provide a netlist-based circuit analysis technique to distinguish so-called critical configuration bits from essential bits in order to identify configuration bits which will need also state-restoring actions after a recovered SEU and which not. Furthermore, b) an alternative classification approach using fault injection is developed in order to compare both classification techniques. Moreover, c) we will propose a floorplanning approach for reducing the effective number of scrubbed frames and d), experimental results will give evidence that our optimization methodology not only allows to detect errors earlier but also to minimize the Mean-Time-To-Repair (MTTR) of a circuit considerably. In particular, we show that by using our approach, the MTTR for datapath-intensive circuits can be reduced by up to 48.5% in comparison to standard approaches

Design and Evaluation of the Efficiency of Channel Coding LDPC Codes for 5G Information Technology

This paper proposes a result of an investigation of a topical problem and the development of models for efficient coding in information networks based on codes with a low density of parity check. The main advantage of the technique is the presented recommendations for choosing a signal-code construction is carried out taking into account the code rate and the number of iterations decoding for envisaging the defined noise immunity indices. The noise immunity of signal-code constructions based on low-density codes has been increased by combining them with multi position digital modulation. This solution eventually allowed to develop a strategy for decoder designing of such codes and to optimize the code structure for a specific information network. To test the effectiveness of the proposed method, MATLAB simulations are carried out under for various Information channels binary symmetric channel (BSC), a channel with additive white Gaussian noise (AWGN), binary asymmetric channel (BAC), asymmetric channel Z type. In addition, different code rates were used during the experiment. The study of signal-code constructions with differential modulation is presented. The efficiency of different decoding algorithms is investigated. The advantage of the obtained results over the known ones consists in determining the maximum noise immunity for the proposed codes. The energy gain was on the order of 6 dB, and an increase in the number of decoding iterations from 3 to 10 leads to a gain in coding energy of 5 dB. Envisaged that the results obtained can be very useful in the development of practical coding schemes in 5G networks

Modelling and analysis of next generation home networks

As Home Networking grows over the next 20 years the need for accurate models for both the network and the hardware becomes apparent. In this work, these two areas are considered together to develop a combined hardware and network model for a HomePlug power line based network. This change of focus is important when the type of devices that will be running on tomorrow's home network is considered. It will have evolved from a simple network of PCs sharing an Internet connection to a large heterogeneous structure of embedded System-on-Chip devices communicating on a variety of linked network technologies.This work presents a novel combined hardware and network modelling tool that address the following areas: 1. Development of a system level model of a HomePlug power-line based network, including the fundamental network protocols, the SoC hardware and the physical channel. 2. Use the developed model to explore various system scenarios. 3. Development of alternative hardware algorithms within the design. The model developed uses a Discrete Event simulation method to allow designers to explore areas such as: 1. How does the networking hardware (i.e. the components on the SoC) interact, and what are the issues of changing the algorithms. 2. I low do the nodes on the network interact, as the traffic patterns are different to those found on traditional (office-based) networks, as there will be a greater amount of streaming media

A methodology for hardware-software codesign

Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (pages 150-156).Special purpose hardware is vital to embedded systems as it can simultaneously improve performance while reducing power consumption. The integration of special purpose hardware into applications running in software is difficult for a number of reasons. Some of the difficulty is due to the difference between the models used to program hardware and software, but great effort is also required to coordinate the simultaneous execution of the application running on the microprocessor with the accelerated kernel(s) running in hardware. To further compound the problem, current design methodologies for embedded applications require an early determination of the design partitioning which allows hardware and software to be developed simultaneously, each adhering to a rigid interface contract. This approach is problematic because often a good hardware-software decomposition is not known until deep into the design process. Fixed interfaces and the burden of reimplementation prevent the migration of functionality motivated by repartitioning. This thesis presents a two-part solution to the integration of special purpose hardware into applications running in software. The first part addresses the problem of generating infrastructure for hardware-accelerated applications. We present a methodology in which the application is represented as a dataflow graph and the computation at each node is specified for execution either in software or as specialized hardware using the programmer's language of choice. An interface compiler as been implemented which takes as input the FIFO edges of the graph and generates code to connect all the different parts of the program, including those which communicate across the hardware/software boundary. This methodology, which we demonstrate on an FPGA platform, enables programmers to effectively exploit hardware acceleration without ever leaving the application space. The second part of this thesis presents an implementation of the Bluespec Codesign Language (BCL) to address the difficulty of experimenting with hardware/software partitioning alternatives. Based on guarded atomic actions, BCL can be used to specify both hardware and low-level software. Based on Bluespec SystemVerilog (BSV) for which a hardware compiler by Bluespec Inc. is commercially available, BCL has been augmented with extensions to support more efficient software generation. In BCL, the programmer specifies the entire design, including the partitioning, allowing the compiler to synthesize efficient software and hardware, along with transactors for communication between the partitions. The benefit of using a single language to express the entire design is that a programmer can easily experiment with many different hardware/software decompositions without needing to re-write the application code. Used together, the BCL and interface compilers represent a comprehensive solution to the task of integrating specialized hardware into an application.by Myron King.Ph.D