Novel Predistortion System for 4G/5G Small-Cell and Wideband Transmitters

To meet the growing demand for mobile data, various technologies are being introduced to wireless networks to increase system capacity. On one hand, large number of small-cell base stations are adopted to serve the reduced cell size; on the other hand, millimeter wave (mm-wave) systems with large antenna arrays that transmit ultra-wideband signals are expected in fifth generation (5G) networks. Power amplifiers (PAs), responsible for boosting the radio frequency (RF) signal power, are the most critical components in base station transmitters, and dominate the overall efficiency and linearity of the system. The design challenges to balance the contradictory requirements of efficiency and linearity of the PAs are usually addressed by linearization techniques, particularly the digital predistortion (DPD) system. However, existing DPD solutions face increasing difficulties keeping up with new developments in base station technologies. When considering sub-6 GHz small-cell base station transmitters, analog and RF predistortion techniques have recently received renewed attention due to their inherent low power nature. Their achievable linearization capacity is significantly limited, however, largely by their implementation complexity in realizing the needed predistortion models in analog circuitry. On the other hand, despite significant developments in DPD models for wideband signals, the implementations of such DPD models in practical hardware have received relatively little attention. Yet the conventional implementation of a DPD engine is limited by the maximum clock frequency of the digital circuitry employed and cannot be scaled to satisfy the growing bandwidth of transmitted signals for 5G networks. Furthermore, both analog and digital solutions require a transmitter-observation-receiver (TOR) to capture the PA outputs, necessitates the use of analog-to-digital converters (ADCs) whose complexity and power consumption increase with signal bandwidth. Such trend is not scalable for future base stations, and new innovations in feedback and training methods are required. This thesis presents a number of contributions to address the above identified challenges. To reduce the power overhead of the linearization system, a digitally-assisted analog-RF predistortion (DA-ARFPD) system that uses a novel predistortion model is introduced. The proposed finite-impulse-response assisted envelope memory polynomial (FIR-EMP) model allows for a reduction of hardware implementation complexity while maintaining good linearization capacity and low power overhead. A two-step small-signal-assisted parameter identification (SSAPI) algorithm is devised to estimate the parameters of the two main blocks of the FIR-EMP model, such that the training can be completed efficiently. A DA-ARFPD test bench has been built, which incorporates major RF components, to assess the validity of the proposed FIR-EMP scheme and the SSAPI algorithm. Measurement results show that the proposed FIR-EMP model with SSAPI algorithm can successfully linearize multiple PAs driven with various wideband and carrier-aggregated signals of up to 80~MHz modulation bandwidths for sub-6 GHz systems. Next, a hardware-efficient real-time DPD system with scalable linearization bandwidth for ultra-wideband 5G mm-wave transmitters is proposed. It uses a novel parallel-processing DPD engine architecture to process multiple samples per clock cycle, overcomes the linearization bandwidth limit imposed by the maximum clock rate of digital circuits used in conventional DPD implementation. Potentially unlimited linearization bandwidth could be achieved by using the proposed system with current digital circuit technologies. The linearization performance and bandwidth scalability of the proposed system is demonstrated experimentally using a silicon-based Doherty (DPA) with 400 MHz wideband signal operating at 28 GHz, and over-the-air measurements using a 64-element beamforming array with 800 MHz wideband signal, also at 28 GHz. The proposed DPD system achieves over 2.4 GHz linearization bandwidth using only a 300 MHz core clock for the digital circuits. Finally, to reduce the power consumption and cost of the TOR, a new approach to train the predistorter using under-sampled feedback signal is presented. Using aliased samples of the PA's output captured at either baseband or intermedia frequency (IF), the proposed algorithm is able to compute the coefficients of the predistortion engine to linearize the PA using a direct learning architecture. Experimentally, both the baseband and IF schemes achieve linearization performance comparable to a full-rate system. Implemented together with a parallel-processing based DPD engine on a field-programmable gate array (FPGA) based system-on-chip (SOC), the proposed feedback and training solution achieves over 2.4~GHz linearization bandwidth using an ADC operating at a clock rate of 200 MHz. Its performance is demonstrated experimentally by linearizing a silicon DPA with 200 MHz and 400 MHz signals in conductive measurements, and a 64-element beamforming array with 400 MHz and 800 MHz signals in over-the-air testing

Behavioral modelling of GaN RF-power amplifier

Abstract. In this thesis memory effects and nonlinearities of Gallium Nitride (GaN) Doherty power amplifier (PA) were studied for measurement based behavioral modelling purposes. In SoC simulations a PA model is needed to simulate the performance of different linearization algorithms and to optimize the digital pre-distortion (DPD) design to cancel the memory effects of the PA, thus the model needs to be capable of modelling the memory effects sufficiently. Aim was to study if there were any differences in power amplifiers behavior and memory effects between time division duplexing (TDD) and frequency division duplexing (FDD) and what kind of model topologies are needed to model the PA sufficiently. In this thesis, two PAs were measured in different operation modes. Characterization setup was built, and an equalizer was characterized to remove the frequency selectivity of the test setup to obtain more accurate measurement results. Two signal bandwidths of 20MHz and 100MHz were used to extract data from power amplifier output with FDD and TDD operation. A generalized memory polynomial was fitted to model the PAs and found to be sufficient to model FDD operation. However, with TDD operation generalized memory polynomial model was not as accurate due to complex memory effects such as thermal and trapping memory. Models were also validated by using a digital pre-distorter and compared with measurement results and the models seem to work well and provide adjacent channel power ratio (ACPR) of -53.5dBc on lower channel and -53.3dBc on upper channel with 100MHz signal.GaN RF-tehovahvistimen käyttäytymistason mallinnus. Tiivistelmä. Tässä työssä tutkittiin Galliumnitraatti (GaN) Doherty-tehovahvistimen (PA) muistiilmiöitä ja epälineaarisuutta mittauksiin perustuvaa käyttäytymistason mallinnusta varten. SoC-simuloinneissa tarvitaan PA-mallia erilaisten linearisointialgoritmien suorituskyvyn simuloimiseksi. Erityisesti digitaalisen esisäröttimen (DPD) suunnittelun optimoimiseksi tehovahvistimessa esiintyvän muistin kumoamiseksi mallin on pystyttävä mallintamaan muistia riittävällä tarkkuudella. Työn tavoitteena oli selvittää, onko tehovahvistimien käyttäytymisessä ja muisti-ilmiöissä eroja aika- ja taajuusdupleksoinnin (TDD, FDD) välillä ja millaisia mallitopologioita tarvitaan, jotta tehovahvistinta voidaan mallintaa riittävällä tarkkuudella. Tässä työssä käytettiin kahta tehovahvistinta eri toimintatilojen mittaamiseen. Työssä rakennettiin mittausympäristö ja lisättiin taajuuskorjain kumoamaan mittausympäristön taajuusselektiivisyyttä. Kahta signaalinkaistanleveyttä 20 MHz:a ja 100 MHz:ä käytettiin datan keräämiseen tehovahvistimen ulostulosta aika- ja taajusjakoista dupleksointia käyttäen. Tehovahvistimen mallintamiseen sovitettiin muistipolynomi, jonka todettiin olevan riittävän tarkka FDD-toiminnan mallintamiseen, mutta TDD-toiminnassa malli ei ollut yhtä tarkka monimutkaisten muisti-ilmiöiden, kuten lämpö- ja elektronien ansoitusmuistin, vuoksi. Mallit validoitiin myös käyttämällä digitaalista esisärötystä ja niitä verrattiin mittaustuloksiin. Mallit näyttävät toimivan hyvin ja tuottavan vierekkäisen kanavan tehosuhteen (ACPR) -53,5dBc alemmalla kanavalla ja -53,3dBc ylemmällä kanavalla 100MHz signaalilla

Efficient, High power Precision RF and mmWave Digital Transmitter Architectures

Digital transmitters offer several advantages over conventional analog transmitters such as reconfigurability, elimination of scaling-unfriendly, power hungry and bulky analog blocks and portability across technology. The rapid advancement of technology in CMOS processes also enables integration of complex digital signal processing circuitry on the same die as the digital transmitter to compensate for their non-idealities. The use of this digital assistance can, for instance, enable the use of highly efficient but nonlinear switching-class power amplifiers by compensating for their severe nonlinearity through digital predistortion. While this shift to digitally intensive transmitter architectures is propelled by the benefits stated above, several pressing challenges arise that vary in their nature depending on the frequency of operation - from RF to mmWave. Millimeter wave CMOS power amplifiers have traditionally been limited in output power due to the low breakdown voltage of scaled CMOS technologies and poor quality of on-chip passives. Moreover, high data-rates and efficient spectrum utilization demand highly linear power amplifiers with high efficiency under back-off. However, linearity and high efficiency are traditionally at odds with each other in conventional power amplifier design. In this dissertation, digital assistance is used to relax this trade-off and enable the use of state-of-the-art switching class power amplifiers. A novel digital transmitter architecture which simultaneously employs aggressive device-stacking and large-scale power combining for watt-class output power, dynamic load modulation for linearization, and improved efficiency under back-off by supply-switching and load modulation is presented. At RF frequencies, while the problem of watt-class power amplification has been long solved, more pressing challenges arise from the crowded spectrum in this regime. A major drawback of digital transmitters is the absence of a reconstruction filter after digital-to-analog conversion which causes the baseband quantization noise to get upconverted to RF and amplified at the output of the transmitter. In high power transmitters, this upconverted noise can be so strong as to prevent their use in FDD systems due to receiver desensitization or impose stringent coexistence challenges. In this dissertation, new quantization noise suppression techniques are presented which, for the first time, contribute toward making watt-class fully-integrated digital RF transmitters a viable alternative for FDD and coexistence scenarios. Specifically, the techniques involve embedding a mixed-domain multi-tap FIR filter within highly-efficient watt-class switching power amplifiers to suppress quantization noise, enhancing the bandwidth of noise suppression, enabling tunable location of suppression and overcoming the limitations of purely digital-domain filtering techniques for quantization noise

Highly efficient linear CMOS power amplifiers for wireless communications

The rapidly expanding wireless market requires low cost, high integration and high performance of wireless communication systems. CMOS technology provides benefits of cost effectiveness and higher levels of integration. However, the design of highly efficient linear CMOS power amplifier that meets the requirement of advanced communication standards is a challenging task because of the inherent difficulties in CMOS technology. The objective of this research is to realize PAs for wireless communication systems that overcoming the drawbacks of CMOS process, and to develop design approaches that satisfying the demands of the industry. In this dissertation, a cascode bias technique is proposed for improving linearity and reliability of the multi-stage cascode CMOS PA. In addition, to achieve load variation immunity characteristic and to enhance matching and stability, a fully-integrated balanced PA is implemented in a 0.18-m CMOS process. A triple-mode balanced PA using switched quadrature coupler is also proposed, and this work saved a large amount of quiescent current and further improved the efficiency in the back-off power. For the low losses and a high quality factor of passive output combining, a transformer-based quadrature coupler was implemented using integrated passive device (IPD) process. Various practical approaches for linear CMOS PA are suggested with the verified results, and they demonstrate the potential PA design approach for WCDMA applications using a standard CMOS technology.PhDCommittee Chair: Kenney, J. Stevenson; Committee Member: Jongman Kim; Committee Member: Kohl, Paul A.; Committee Member: Kornegay, Kevin T.; Committee Member: Lee, Chang-H

Mixed-Signal Multimode Radio Software/Hardware Development Platform

Radio frequency power amplifiers (PAs) are the most challenging part of the design of radio systems since they dictate the overall system's performance in terms of power efficiency and distortion generation. The performance is further challenged by modern modulation schemes which are characterized by highly varying signal envelopes. In order to meet the spectrum mask requirements, PAs are usually operated at high power back-off to ensure linearity, at the cost of efficiency. To tackle this issue, many efficiency enhancement techniques have been presented in the literature. In fact, these techniques do increase the PA power efficiency at back-off, however, efficiency enhancement techniques do not ensure the linearity of the PA. Furthermore, these techniques may lead to additional distortion. On the other hand, several linearization techniques have been developed to mitigate the PA nonlinearity problem and allow the PA to operate at less back-off. Digital Pre-Distortion (DPD) technique is gaining more attention, as compared to other linearization techniques, thanks to its simple concept and advancements in digital signal processors (DSP) and signal converters. DPD technique consists of introducing a nonlinear function before the PA so that the overall cascaded system behaves linearly. It was clear from the literature that this technique showed good performance. Yet, it has primarily been validated using commercial test equipment, which has good capabilities, and far from the real world environment in which this technique would be implemented. Indeed, DPDs would need to be implemented in signal processors characterised by limited resources and computational accuracy. This thesis presents an implementation of several DPD models, namely look-up table (LUT), memoryless polynomial and memory polynomial (MP), on a field programmable gate array (FPGA). A novel model reformulation made this implementation possible in fixed-point arithmetic. Measurements were collected to validate the DPD models' implementation and an improvement of the signal quality was recorded in terms of error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR). As many wireless access technologies must continue to coexist, multi-standard radio systems are required to reduce the cost while maintaining the interoperability. This thesis presents a development platform for multimode radio which comprises mixed-signal modules. The platform provides the capacity for hardware and software development. In fact, the FPGA under investigation allowed for the implementation of a baseband transceiver and DPD schemes. In addition, a software tool was developed as a dashboard to control and monitor the system. The radio system in the platform was optimized through the equalization of the feedback receiver frequency response performed through a simultaneous measurement of the amplitude ripple of the transmitter and receiver. Furthermore, a phase-coherent frequency synthesizer was designed to bring more flexibility by allowing the transmitter's carrier frequency to be different from the receiver's frequency

Electronically reconfigurable wideband high-power amplifier architecture for modern RF systems (LMBA)

As mobile communications and other microwave systems continue to evolve designers and system architects are pushing for ever increasing bandwidth as multiple RF systems are increasingly sharing a common front-end amplifier to save space and reduce routing complexity and losses associated with having separate amplifier systems. The power amplifier in many RF systems typically accounts for the majority of the power consumption of the device or transmitter platform, it is therefore paramount that to improve the efficiency of these systems RFPA designs must be tailored to achieve the highest possible efficiency. RFPA modes of operation and architectures to achieve higher efficiency have been developed, but often come with compromises to other system aspects such as linearity, control complexity and most commonly bandwidth. With the next generation 5G communications specification including frequency bands of up to the Ka frequency spectrum and the high capacity multi-octave spectrum bands allocated at L-C band, traditional RFPA efficiency enhancement techniques struggle to be implementable due to either the high frequency requirements of the control systems needed or due to the bandwidth restrictions of such techniques. II Conventionally narrow bandwidth X-band radar systems that used to be operated at saturated output power conditions are starting to explore multimode operation that require more power back-off (PBO) and control of the RFPA, so are searching for techniques that are applicable at X-band and can achieve the same level of PBO requirements demanded by modern communication modulation standards while working to the power and cooling restraints that come from a limited application platform such as fighter aircraft. Similarly, such fighter platforms are demanding increased electronic warfare (EW) capability which are restrained to the same platform limitations but often need to cover multi-octave bandwidths where traditional efficiency enhancement techniques cannot be applied. This research will focus on wideband efficiency enhancement for both saturated and PBO scenarios that present a frequency agnostic technique of overcoming conventional limitations. The novel work presented is based around the quintessential, but relatively old, bandwidth extension architecture known as the balanced amplifier. The addition of a secondary control signal has been proposed whereby the operating impedance of the amplifier can be dramatically modulated while maintaining the fundamental advantage the balanced amplifier allow, that is multi-octave bandwidth. III The power of this architecture can draw similarities in impedance control afforded by load pull systems, in particular active load-pull. With the correct control signal, any impedance is able to be presented to the transistors to keep them operating at maximum efficiency, where passive matching alone is not able to achieve such efficiency due to fundamental matching theory. Due to the active element of this novel architecture, named the Load Modulated Balanced Amplifier (LMBA), frequency restrictive and thus band limiting elements present in other efficiency enhancement techniques; such as the quarter wave inverter present in the Doherty Amplifier or the difficulty of realizing the modulator in Envelope Tracking (ET) are not present. This thesis will present the fundamental theory driving the operation of an LMBA along with multiple implementations, each targeted at differing applications and different frequency bands to demonstrate the versatility and frequency independence of the technique

Electronically reconfigurable wideband high-power amplifier architecture for modern RF systems (LMBA)

As mobile communications and other microwave systems continue to evolve designers and system architects are pushing for ever increasing bandwidth as multiple RF systems are increasingly sharing a common front-end amplifier to save space and reduce routing complexity and losses associated with having separate amplifier systems. The power amplifier in many RF systems typically accounts for the majority of the power consumption of the device or transmitter platform, it is therefore paramount that to improve the efficiency of these systems RFPA designs must be tailored to achieve the highest possible efficiency. RFPA modes of operation and architectures to achieve higher efficiency have been developed, but often come with compromises to other system aspects such as linearity, control complexity and most commonly bandwidth. With the next generation 5G communications specification including frequency bands of up to the Ka frequency spectrum and the high capacity multi-octave spectrum bands allocated at L-C band, traditional RFPA efficiency enhancement techniques struggle to be implementable due to either the high frequency requirements of the control systems needed or due to the bandwidth restrictions of such techniques. II Conventionally narrow bandwidth X-band radar systems that used to be operated at saturated output power conditions are starting to explore multimode operation that require more power back-off (PBO) and control of the RFPA, so are searching for techniques that are applicable at X-band and can achieve the same level of PBO requirements demanded by modern communication modulation standards while working to the power and cooling restraints that come from a limited application platform such as fighter aircraft. Similarly, such fighter platforms are demanding increased electronic warfare (EW) capability which are restrained to the same platform limitations but often need to cover multi-octave bandwidths where traditional efficiency enhancement techniques cannot be applied. This research will focus on wideband efficiency enhancement for both saturated and PBO scenarios that present a frequency agnostic technique of overcoming conventional limitations. The novel work presented is based around the quintessential, but relatively old, bandwidth extension architecture known as the balanced amplifier. The addition of a secondary control signal has been proposed whereby the operating impedance of the amplifier can be dramatically modulated while maintaining the fundamental advantage the balanced amplifier allow, that is multi-octave bandwidth. III The power of this architecture can draw similarities in impedance control afforded by load pull systems, in particular active load-pull. With the correct control signal, any impedance is able to be presented to the transistors to keep them operating at maximum efficiency, where passive matching alone is not able to achieve such efficiency due to fundamental matching theory. Due to the active element of this novel architecture, named the Load Modulated Balanced Amplifier (LMBA), frequency restrictive and thus band limiting elements present in other efficiency enhancement techniques; such as the quarter wave inverter present in the Doherty Amplifier or the difficulty of realizing the modulator in Envelope Tracking (ET) are not present. This thesis will present the fundamental theory driving the operation of an LMBA along with multiple implementations, each targeted at differing applications and different frequency bands to demonstrate the versatility and frequency independence of the technique

Contributing to Second Harmonic Manipulated Continuum Mode Power Amplifiers and On-Chip Flux Concentrators

The current cellular network consumes a staggering 100 TWh of energy every year. In the coming years, millions of devices will be added to the existing network to realize the Internet of Things (IoT), further increasing its power consumption. An RF power amplifier typically consumes a large proportion of the DC power in a wireless transceiver, improving its efficiency has the largest impact on the overall system. Additionally, amplifiers need to demonstrate high linearity and bandwidth to adhere to constraints imposed by wireless standards and to reduce the number of amplifiers required as an amplifier with a broader bandwidth can potentially replace several narrowband amplifiers. A typical approach to improve efficiency is to present an appropriate load at the harmonics generated by the transistor. Recently proposed continuous modes based on harmonic manipulation, such as class B/J continuum, continuous class F (CCF) and continuous class F-1 (CCF-1), have shown the capability of achieving counteracting requirements viz., high efficiency, high linearity, and broad bandwidth (with a fractional bandwidth greater than 30%). In these classes of amplifiers, the second harmonic is manipulated by placing a reactive second harmonic load and the reactive component of the fundamental load is adjusted while keeping a fixed resistive component of the fundamental load. The first contribution of this work is to investigate the reason for amplifiers designed in classes B/J continuum and CCF to achieve high efficiency at back-off and 1dB compression. In this thesis, we demonstrate that the variation of the phase of the current through the non-linear intrinsic capacitances due to the variation of the phase in the continuum of drain voltage waveforms in Class B/J/J* continuum leads to either a reduction or enhancement of intrinsic drain current. Consequently, a subset of voltage waveforms of the class B/J/J* continuum can be used to design amplifiers with higher P1dB, and efficiency at P1dB than in Class B. A simple choice of this subset is demonstrated with a 2.6GHz Class B/J/J* amplifier, achieving a P1dB of 38.1dBm and PAE at P1dB of 54.7%, the highest output power and efficiency at P1dB amongst narrowband linear amplifiers using the CGH40010 reported to date, at a comparable peak PAE of 72%. Secondly, we propose a new formulation for high-efficiency modes of power amplifiers in which both the in-phase and out-of-phase components of the second harmonic of the current are varied, in addition to the second harmonic component of the voltage. A reduction of the in-phase component of the second harmonic of current allows reduction of the phase difference between the voltage and current waveforms, thereby increasing the power factor and efficiency. Our proposed waveforms offer a continuous design space between class B/J continuum and continuous F-1 achieving an efficiency of up to 91% in theory, but over a wider set of load impedances than continuous class F-1. These waveforms require a short at third and higher harmonic impedances, which are easier to achieve at a higher frequency. The load impedances at the second harmonic are reactive and can be of any value between -j∞ and j∞, easing the amplifier design. A trade-off between linearity and efficiency exists in the newly proposed broadband design space, but we demonstrate inherent broadband capability. The fabricated narrowband amplifier using a GaN HEMT CGH40010F demonstrates 75.9% PAE and 42.2 dBm output power at 2.6 GHz, demonstrating a comparable frequency weighted efficiency for this device to that reported in the literature. IoT devices may be deployed in critical applications such as radar or 5G transceivers of an autonomous vehicle and hence need to operate free of failure. Monitoring the drain current of the RF GaN MMIC would allow to optimize the device performance and protect it from surges in its supply current. Galvanic current sensors rely on the magnetic field generated by the current as a non-invasive method of current sensing. In this thesis, our third major contribution is a planar on-chip magnetic flux concentrator, is enhance the magnetic field at the current sensor, thereby improving the current detection capability of a current sensor. Our layout utilizes a discontinuity in a magnetic via, resulting in penetration of the magnetic field into the substrate. The proposed concentrator has a magnetic gain x1.8 in comparison to air. The permeability of the magnetic core required is 500, much lower than that reported in off-chip concentrators, resulting in a significant easing of the specifications of the material properties of the core. Additionally, we explore a novel three-dimensional spiral-shaped magnetic flux concentrator. It is predicted via simulations that this geometry becomes a necessity to enhance the magnetic field for increased form factor as the magnetic field from a single planar concentrator deteriorates as its size increases

LINC based amplifier architectures for power efficient wireless transmitters

Wireless communication trends Performance measuring of a communication system Power amplifiers and transmitters Power efficiency enhancement techniques Design and Optimization of LINC transmitter for OFDM applications LINC concept LINC signal decomposition LINC efficiency and combiner technologies Design optimization of LINC system Mismatch (imbalance) effects Advanced LINC transmitter architectures The 2X1 LINC transmitter system The 2X2 LINC transmitter system Mismatch effects