7,624 research outputs found
NoCo: ILP-based worst-case contention estimation for mesh real-time manycores
Manycores are capable of providing the computational demands required by functionally-advanced critical applications in domains such as automotive and avionics. In manycores a network-on-chip (NoC) provides access to shared caches and memories and hence concentrates most of the contention that tasks suffer, with effects on the worst-case contention delay (WCD) of packets and tasks' WCET. While several proposals minimize the impact of individual NoC parameters on WCD, e.g. mapping and routing, there are strong dependences among these NoC parameters. Hence, finding the optimal NoC configurations requires optimizing all parameters simultaneously, which represents a multidimensional optimization problem. In this paper we propose NoCo, a novel approach that combines ILP and stochastic optimization to find NoC configurations in terms of packet routing, application mapping, and arbitration weight allocation. Our results show that NoCo improves other techniques that optimize a subset of NoC parameters.This work has been partially supported by the Spanish Ministry of Economy and Competitiveness under grant TIN2015-
65316-P and the HiPEAC Network of Excellence. It also received funding from the European Research Council (ERC) under the European Unionâs Horizon 2020 research and innovation programme (agreement No. 772773). Carles HernĂĄndez
is jointly supported by the MINECO and FEDER funds
through grant TIN2014-60404-JIN. Jaume Abella has been
partially supported by the Spanish Ministry of Economy and
Competitiveness under Ramon y Cajal postdoctoral fellowship
number RYC-2013-14717. Enrico Mezzetti has been partially
supported by the Spanish Ministry of Economy and Competitiveness
under Juan de la Cierva-IncorporaciÂŽon postdoctoral
fellowship number IJCI-2016-27396.Peer ReviewedPostprint (author's final draft
On quantifying fault patterns of the mesh interconnect networks
One of the key issues in the design of Multiprocessors System-on-Chip (MP-SoCs), multicomputers, and peerto- peer networks is the development of an efficient communication network to provide high throughput and low latency and its ability to survive beyond the failure of individual components. Generally, the faulty components may be coalesced into fault regions, which are classified into convex and concave shapes. In this paper, we propose a mathematical solution for counting the number of common fault patterns in a 2-D mesh interconnect network including both convex (|-shape, | |-shape, ĂÂœ-shape) and concave (L-shape, Ushape, T-shape, +-shape, H-shape) regions. The results presented in this paper which have been validated through simulation experiments can play a key role when studying, particularly, the performance analysis of fault-tolerant routing algorithms and measure of a network fault-tolerance expressed as the probability of a disconnection
Mapping and Scheduling in Heterogeneous NoC through Population-Based Incremental Learning
ABSTRACT: Network-on-Chip (NoC) is a growing and promising communication paradigm
for Multiprocessor-System-On-Chip (MPSoC) design, because of its scalability
and performance features. In designing such systems, mapping and scheduling are becoming
critical stages, because of the increase of both size of the network and applicationâs
complexity. Some reported solutions solve each issue independently. However,
a conjoint approach for solving mapping and scheduling allows to take into account
both computation and communication objectives simultaneously. This paper shows a
mapping and scheduling solution, which is based on a Population-Based Incremental
Learning (PBIL) algorithm. The simulation results suggest that our PBIL approach
is able to find optimal mapping and scheduling, in a multi-objective fashion. A 2-D
heterogeneous mesh was used as target architecture for implementation, although the
PBIL representation is suited to deal with more complex architectures, such as 3-D
meshes
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