A 25% Tuning Range 7.5-9.4 GHz Oscillator With 194 FoM_Tand 400 kHz 1/f Corner in 40nm CMOS Technology

An 8-GHz VCO with class-F23 operation was realized in a 40 nm CMOS technology without ultra-thick metals. The class-F23 operation was enabled in a transformer-based LC tank to allow multiple impedance peaks in the common mode (CM) and the differential mode (DM) excitation. With the additional resonance at $2^{nd}$ and $3^{rd}$ harmonic frequency, the circuit noise to phase-noise conversion and 1/f noise up-conversion are reduced significantly. In a 40 nm CMOS technology without ultra-thick metal, a patterned shielding structure was proposed to improve the inductor quality factor. A combined varactor and capacitor array is proposed to provide accurate matching for a desired resonance frequency ratio, reducing AM-FM conversion and it achieves a broad tuning range. With the proposed transformer-based LC bank and class-F23 operation, the oscillator achieves a phase noise of -150.8 dBc/Hz at 10 MHz offset from a 1.85 GHz carrier after an on-chip /4 divider, and the measured 1/f3 flicker noise corner is around 400 kHz. The oscillator core covers a 7.5-9.4 GHz frequency range for a 25% tuning range.</p

Low-Voltage Ultra-Low-Power Current Conveyor Based on Quasi-Floating Gate Transistors

The field of low-voltage low-power CMOS technology has grown rapidly in recent years; it is an essential prerequisite particularly for portable electronic equipment and implantable medical devices due to its influence on battery lifetime. Recently, significant improvements in implementing circuits working in the low-voltage low-power area have been achieved, but circuit designers face severe challenges when trying to improve or even maintain the circuit performance with reduced supply voltage. In this paper, a low-voltage ultra-low-power current conveyor second generation CCII based on quasi-floating gate transistors is presented. The proposed circuit operates at a very low supply voltage of only ±0.4 V with rail-to-rail voltage swing capability and a total quiescent power consumption of mere 9.5 µW. Further, the proposed circuit is not only able to process the AC signal as it's usual at quasi-floating gate transistors but also the DC which extends the applicability of the proposed circuit. In conclusion, an application example of the current-mode quadrature oscillator is presented. PSpice simulation results using the 0.18 µm TSMC CMOS technology are included to confirm the attractive properties of the proposed circuit

An Ultra-Low-Power Oscillator with Temperature and Process Compensation for UHF RFID Transponder

This paper presents a 1.28MHz ultra-low-power oscillator with temperature and process compensation. It is very suitable for clock generation circuits used in ultra-high-frequency (UHF) radio-frequency identification (RFID) transponders. Detailed analysis of the oscillator design, including process and temperature compensation techniques are discussed. The circuit is designed using TSMC 0.18μm standard CMOS process and simulated with Spectre. Simulation results show that, without post-fabrication calibration or off-chip components, less than ±3% frequency variation is obtained from –40 to 85°C in three different process corners. Monte Carlo simulations have also been performed, and demonstrate a 3σ deviation of about 6%. The power for the proposed circuitry is only 1.18µW at 27°C

PVT-Robust CMOS Programmable Chaotic Oscillator: Synchronization of Two 7-Scroll Attractors

Designing chaotic oscillators using complementary metal-oxide-semiconductor (CMOS) integrated circuit technology for generating multi-scroll attractors has been a challenge. That way, we introduce a current-mode piecewise-linear (PWL) function based on CMOS cells that allow programmable generation of 2–7-scroll chaotic attractors. The mathematical model of the chaotic oscillator designed herein has four coefficients and a PWL function, which can be varied to provide a high value of the maximum Lyapunov exponent. The coefficients are implemented electronically by designing operational transconductance amplifiers that allow programmability of their transconductances. Design simulations of the chaotic oscillator are provided for the 0.35μ m CMOS technology. Post-layout and process–voltage–temperature (PVT) variation simulations demonstrate robustness of the multi-scroll chaotic attractors. Finally, we highlight the synchronization of two seven-scroll attractors in a master–slave topology by generalized Hamiltonian forms and observer approach. Simulation results show that the synchronized CMOS chaotic oscillators are robust to PVT variations and are suitable for chaotic secure communication applications.Universidad Autónoma de Tlaxcala CACyPI-UATx-2017Program to Strengthen Quality in Educational Institutions C/PFCE-2016-29MSU0013Y-07-23National Council for Science and Technology 237991 22284

A New Technique for the Design of Multi-Phase Voltage Controlled Oscillators

© 2017 World Scientific Publishing Company.In this work, a novel circuit structure for second-harmonic multi-phase voltage controlled oscillator (MVCO) is presented. The proposed MVCO is composed of (Formula presented.) ((Formula presented.) being an integer number and (Formula presented.)2) identical inductor–capacitor ((Formula presented.)) tank VCOs. In theory, this MVCO can provide 2(Formula presented.) different phase sinusoidal signals. A six-phase VCO based on the proposed structure is designed in a TSMC 0.18(Formula presented.)um CMOS process. Simulation results show that at the supply voltage of 0.8(Formula presented.)V, the total power consumption of the six-phase VCO circuit is about 1(Formula presented.)mW, the oscillation frequency is tunable from 2.3(Formula presented.)GHz to 2.5(Formula presented.)GHz when the control voltage varies from 0(Formula presented.)V to 0.8(Formula presented.)V, and the phase noise is lower than (Formula presented.)128(Formula presented.)dBc/Hz at 1(Formula presented.)MHz offset frequency. The proposed MVCO has lower phase noise, lower power consumption and more outputs than other related works in the literature.Peer reviewedFinal Accepted Versio

Hysteresis based neural oscillators for VLSI implementations

The actual tendency in most of the work that is being done in VLSI neural network research is to use the simplest possible models to perform the desired tasks. This yields to the use of sigmoidal type neurons that have a static input-output relationship. However, in some cases, especially when the research is close to biological neuron systems emulation, such simplifled models are not always valid. In these cases, a neuron model closer to biological neurons is needed, namely the oscillatory neuron [l-41. For these neurons, when they are active, their output is a sequence of pulses. In this paper we present several circuits that can be set in an active state to yield an oscillatory output. The difference between the circuits is based on whether the output has two unique output states (off, or on flring at a specific frequency), or has a continuum between the on and off states so t h a t the output frequency changes sigmoidally between zero and its maximum

1 V CMOS subthreshold log domain PDM

A new CMOS circuit strategy for very low-voltage Pulse-Duration Modulators (PDM) is proposed. Optimization of voltage supply scaling below the sum of threshold voltages is based on Instantaneous Log Companding processing through the MOSFET operating in weak inversion. A 1 V VLSI PDM circuit for very low-voltage audio applications such as Hearing Aids is presented, showing good agreement between simulated and experimental data.Comisión Interministerial de Ciencia y Tecnología TIC97-1159, TIC99-1084European Union 2306

A general theory of phase noise in electrical oscillators

A general model is introduced which is capable of making accurate, quantitative predictions about the phase noise of different types of electrical oscillators by acknowledging the true periodically time-varying nature of all oscillators. This new approach also elucidates several previously unknown design criteria for reducing close-in phase noise by identifying the mechanisms by which intrinsic device noise and external noise sources contribute to the total phase noise. In particular, it explains the details of how 1/f noise in a device upconverts into close-in phase noise and identifies methods to suppress this upconversion. The theory also naturally accommodates cyclostationary noise sources, leading to additional important design insights. The model reduces to previously available phase noise models as special cases. Excellent agreement among theory, simulations, and measurements is observed

A 12MHz Switched-Capacitor Relaxation Oscillator with a Nearly Minimal FoM of -161dBc/Hz

In this work the phase noise performance of relaxation oscillators has been analyzed resulting in simple though precise phase noise expressions. These expressions have lead to a new relaxation oscillator topology, which exploits a noise filtering technique implemented with a switched-capacitor circuit to minimize phase noise. Measurements on a 65nm CMOS design show a sawtooth waveform, a frequency tuning range between 1 and 12MHz and a rather constant frequency tuning gain. At 12MHz oscillation frequency it consumes 90μW while the phase noise is -109dBc/Hz at 100KHz offset frequency. By minimizing and balancing noise contributions of charge and discharge mechanisms, a nearly minimal FoM of -161dBc/Hz has been achieved, which is a 6dB improvement over state-of-the-art

Near-Zero-Power Temperature Sensing via Tunneling Currents Through Complementary Metal-Oxide-Semiconductor Transistors.

Temperature sensors are routinely found in devices used to monitor the environment, the human body, industrial equipment, and beyond. In many such applications, the energy available from batteries or the power available from energy harvesters is extremely limited due to limited available volume, and thus the power consumption of sensing should be minimized in order to maximize operational lifetime. Here we present a new method to transduce and digitize temperature at very low power levels. Specifically, two pA current references are generated via small tunneling-current metal-oxide-semiconductor field effect transistors (MOSFETs) that are independent and proportional to temperature, respectively, which are then used to charge digitally-controllable banks of metal-insulator-metal (MIM) capacitors that, via a discrete-time feedback loop that equalizes charging time, digitize temperature directly. The proposed temperature sensor was integrated into a silicon microchip and occupied 0.15 mm2 of area. Four tested microchips were measured to consume only 113 pW with a resolution of 0.21 °C and an inaccuracy of ±1.65 °C, which represents a 628× reduction in power compared to prior-art without a significant reduction in performance