Blocker Tolerant Radio Architectures

Future radio platforms have to be inexpensive and deal with a variety of co- existence issues. The technology trend during the last few years is towards system- on-chip (SoC) that is able to process multiple standards re-using most of the digital resources. A major bottle-neck to this approach is the co-existence of these standards operating at different frequency bands that are hitting the receiver front-end. So the current research is focused on the power, area and performance optimization of various circuit building blocks of a radio for current and incoming standards. Firstly, a linearization technique for low noise amplifiers (LNAs) called, Robust Derivative Superposition (RDS) method is proposed. RDS technique is insensitive to Process Voltage and Temperature (P.V.T.) variations and is validated with two low noise transconductance amplifier (LNTA) designs in 0.18µm CMOS technology. Measurement results from 5 dies of a resistive terminated LNTA shows that the pro- posed method improves IM3 over 20dB for input power up to -18dBm, and improves IIP_(3) by 10dB. A 2V inductor-less broadband 0.3 to 2.8GHz balun-LNTA employing the proposed RDS linearization technique was designed and measured. It achieves noise figure of 6.5dB, IIP3 of 16.8dBm, and P1dB of 0.5dBm having a power consumption of 14.2mW. The balun LNTA occupies an active area of 0.06mm2. Secondly, the design of two high linearity, inductor-less, broadband LNTAs employing noise and distortion cancellation techniques is presented. Main design issues and the performance trade-offs of the circuits are discussed. In the fully differential architecture, the first LNTA covers 0.1-2GHz bandwidth and achieves a minimum noise figure (NFmin) of 3dB, IIP_(3) of 10dBm and a P_(1dB) of 0dBm while dissipating 30.2mW. The 2^(nd) low power bulk driven LNTA with 16mW power consumption achieves NFmin of 3.4dB, IIP3 of 11dBm and 0.1-3GHz bandwidth. Each LNTA occupy an active area of 0.06mm2 in 45nm CMOS. Thirdly, a continuous-time low-pass ∆ΣADC equipped with design techniques to provide robustness against loop saturation due to blockers is presented. Loop over- load detection and correction is employed to improve the ADC’s tolerance to blockers; a fast overload detector activates the input attenuator, maintaining the ADC in linear operation. To further improve ADC’s blocker tolerance, a minimally-invasive integrated low-pass filter that reduces the most critical adjacent/alternate channel blockers is implemented. An ADC prototype is implemented in a 90nm CMOS technology and experimentally it achieves 69dB dynamic range over a 20MHz bandwidth with a sampling frequency of 500MHz and 17.1mW of power consumption. The alternate channel blocker tolerance at the most critical frequency is as high as -5.5dBFS while the conventional feed-forward modulator becomes unstable at -23.5dBFS of blocker power. The proposed blocker rejection techniques are minimally-invasive and take less than 0.3µsec to settle after a strong agile blocker appears. Finally, a new radio partitioning methodology that gives robust analog and mixed signal radio development in scaled technology for SoC integration, and the co-design of RF FEM-antenna system is presented. Based on the proposed methodology, a CMOS RF front-end module (FEM) with power amplifier (PA), LNA and transmit/receive switch, co-designed with antenna is implemented. The RF FEM circuit is implemented in a 32nm CMOS technology. Post extracted simulations show a noise figure < 2.5dB, S_(21) of 14dB, IIP3 of 7dBm and P1dB of -8dBm for the receiver. Total power consumption of the receiver is 11.8mW from a 1V supply. On the trans- mitter side, PA achieves peak RF output power of 22.34dBm with peak power added efficiency (PAE) of 65% and PAE of 33% with linearization at -6dB power back off. Simulations show an efficiency of 80% for the miniaturized dipole antenna

CMOS Integrated Power Amplifiers for RF Reconfigurable and Digital Transmitters

abstract: This dissertation focuses on three different efficiency enhancement methods that are applicable to handset applications. These proposed designs are based on three critical requirements for handset application: 1) Small form factor, 2) CMOS compatibility and 3) high power handling. The three presented methodologies are listed below: 1) A transformer-based power combiner architecture for out-phasing transmitters 2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA) 3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB. The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%. Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Efficient, High power Precision RF and mmWave Digital Transmitter Architectures

Digital transmitters offer several advantages over conventional analog transmitters such as reconfigurability, elimination of scaling-unfriendly, power hungry and bulky analog blocks and portability across technology. The rapid advancement of technology in CMOS processes also enables integration of complex digital signal processing circuitry on the same die as the digital transmitter to compensate for their non-idealities. The use of this digital assistance can, for instance, enable the use of highly efficient but nonlinear switching-class power amplifiers by compensating for their severe nonlinearity through digital predistortion. While this shift to digitally intensive transmitter architectures is propelled by the benefits stated above, several pressing challenges arise that vary in their nature depending on the frequency of operation - from RF to mmWave. Millimeter wave CMOS power amplifiers have traditionally been limited in output power due to the low breakdown voltage of scaled CMOS technologies and poor quality of on-chip passives. Moreover, high data-rates and efficient spectrum utilization demand highly linear power amplifiers with high efficiency under back-off. However, linearity and high efficiency are traditionally at odds with each other in conventional power amplifier design. In this dissertation, digital assistance is used to relax this trade-off and enable the use of state-of-the-art switching class power amplifiers. A novel digital transmitter architecture which simultaneously employs aggressive device-stacking and large-scale power combining for watt-class output power, dynamic load modulation for linearization, and improved efficiency under back-off by supply-switching and load modulation is presented. At RF frequencies, while the problem of watt-class power amplification has been long solved, more pressing challenges arise from the crowded spectrum in this regime. A major drawback of digital transmitters is the absence of a reconstruction filter after digital-to-analog conversion which causes the baseband quantization noise to get upconverted to RF and amplified at the output of the transmitter. In high power transmitters, this upconverted noise can be so strong as to prevent their use in FDD systems due to receiver desensitization or impose stringent coexistence challenges. In this dissertation, new quantization noise suppression techniques are presented which, for the first time, contribute toward making watt-class fully-integrated digital RF transmitters a viable alternative for FDD and coexistence scenarios. Specifically, the techniques involve embedding a mixed-domain multi-tap FIR filter within highly-efficient watt-class switching power amplifiers to suppress quantization noise, enhancing the bandwidth of noise suppression, enabling tunable location of suppression and overcoming the limitations of purely digital-domain filtering techniques for quantization noise

Linearization and Efficiency Enhancement Techniques for RF and Baseband Analog Circuits

High linearity transmitters and receivers should be used to efficiently utilize the available channel bandwidth. Power consumption is also a critical factor that determines the battery life of portable devices and wireless sensors. Three base-band and RF building blocks are designed with the focus of high linearity and low power consumption. An architectural attenuation-predistortion linearization scheme for a wide range of operational transconductance amplifiers (OTAs) is proposed and demonstrated with a transconductance-capacitor (Gm-C) filter. The linearization technique utilizes two matched OTAs to cancel output harmonics, creating a robust architecture. Compensation for process variations and frequency-dependent distortion based on Volterra series analysis is achieved by employing a delay equalization scheme with on-chip programmable resistors. The distortion-cancellation technique enables an IM3 improvement of up to 22dB compared to a commensurate OTA without linearization. A proof-of-concept lowpass filter with the linearized OTAs has a measured IM3 < -70dB and 54.5dB dynamic range over its 195MHz bandwidth. Design methodology for high efficiency class D power amplifier is presented. The high efficiency is achieved by using higher current harmonic to achieve zero voltage switching (ZVS) in class D power amplifier. The matching network is used as a part of the output filter to remove the high order harmonics. Optimum values for passive circuit elements and transistor sizes have been derived in order to achieve the highest possible efficiency. The proposed power amplifier achieves efficiency close to 60 percent at 400 MHz for -2dBm of output power. High efficiency class A power amplifier using dynamic biasing technique is presented. The power consumption of the power amplifier changes dynamically according to the output signal level. Effect of dynamic bias on class A power amplifier linearity is analyzed and the results were verified using simulations. The linearity of the dynamically biased amplifier is improved by adjusting the preamplifier gain to guarantee constant overall gain for different input signal levels

CMOS RF Power Amplifiers for Wireless Communications

The wireless market has experienced a remarkable development and growth since the introduction of the first modern mobile phone systems, with a steady increase in the number of subscribers, new application areas, and higher data rates. As mobile phones and wireless connectivity have become consumer mass markets, the prime goal of the IC manufacturers is to provide low-cost solutions. The power amplifier (PA) is a key building block in all RF transmitters. To lower the costs and allow full integration of a complete radio System-on-Chip (SoC), it is desirable to integrate the entire transceiver and the PA in a single CMOS chip. While digital circuits benefit from the technology scaling, it is becoming harder to meet the stringent requirements on linearity, output power, bandwidth, and efficiency at lower supply voltages in traditional PA architectures. This has recently triggered extensive studies to investigate the impact of different efficiency enhancement and linearization techniques, like polar modulation and outphasing, in nanometer CMOS technologies. This thesis addresses the potential of integrating linear and power-efficient PAs in nanometer CMOS technologies at GHz frequencies. In total eight amplifiers have been designed - two linear Class-A PAs, two switched Class-E PAs, and four Class-D PAs linearized in outphasing configurations. Based on the outphasing PAs, amplifier models and predistorters have been developed and evaluated for uplink (terminal) and downlink (base station) signals. The two linear Class-A PAs with LC-based and transformer-based input and interstage matching networks were designed in a 65nm CMOS technology for 2.4GHz 802.11n WLAN. For a 72.2Mbit/s 64-QAM 802.11n OFDM signal with PAPR of 9.1dB, both PAs fulfilled the toughest EVM requirement in the standard at average output power levels of +9.4dBm and +11.6dBm, respectively. The two PAs were among the first PAs implemented in a 65nm CMOS technology. The two Class-E PAs, intended for DECT and Bluetooth, were designed in 130nm CMOS and operated at low ‘digital’ supply voltages. The PAs delivered +26.4 and +22.7dBm at 1.5V and 1.0V supply voltages with PAE of 30% and 36%, respectively. The Bluetooth PA was based on thin oxide devices and the performance degradation over time for a high level of oxide stress was evaluated. The four Class-D outphasing PAs were designed in 65nm, 90nm, and 130nm CMOS technologies. The first outphasing design was based on a Class-D stage utilizing a cascode configuration, driven by an AC-coupled low-voltage driver, to allow a 5.5V supply voltage in a 65nm CMOS technology without excessive device voltage stress. Two on-chip transformers combined the outputs of four Class-D stages. At 1.95GHz the PA delivered +29.7dBm with a PAE of 26.6%. The 3dB bandwidth was  1.6GHz, representing state-of-the-art bandwidth for CMOS Class-D RF PAs. After one week of continuous operation, no performance degradation was noticed. The second design was based on the same Class-D stage, but combined eight amplifier stages by four on-chip transformers in 130nm CMOS to achieve a state-of-the-art output power of +32dBm for CMOS Class-D RF PAs. Both designs met the ACLR and modulation requirements without predistortion when amplifying uplink WCDMA and 20MHz LTE signals. The third outphasing design was based on two low-power Class-D stages in 90nm CMOS featuring a harmonic suppression technique, cancelling the third harmonic in the output spectrum which also improves drain efficiency. The proposed Class-D stage creates a voltage level of VDD/2 from a single supply voltage to shape the drain voltage, uses only digital circuits and eliminates the short-circuit current present in inverter-based Class-D stages. A single Class-D stage delivered +5.1dBm at 1.2V supply voltage with a drain efficiency and PAE of 73% and 59%, respectively. Two Class-D stages were connected to a PCB transformer to create an outphasing amplifier, which was linear enough to amplify EDGE and WCDMA signals without the need for predistortion. The fourth outphasing design was based on two Class-D stages  connected to an on-chip transformer with peak power of +10dBm. It was used in the development of a behavioral model structure and model-based phase-only predistortion method suitable for outphasing amplifiers to compensate for both amplitude and phase mismatches. In measurements for EDGE and WCDMA signals, the predistorter improved the margin to the limits of the spectral mask and the ACLR by more than 12dB. Based on a similar approach, an amplifier model and predistortion method were developed and evaluated for the +32dBm Class-D PA design using a downlink WCDMA signal, where the ACLR was improved by 13.5dB. A least-squares phase predistortion method was developed and evaluated for the +30dBm Class-D PA design using WCDMA and LTE uplink signals, where the ACLR was improved by approximately 10dB